Physical Design Engineering, VP
Astera Labs · San Jose, CA · 1 mo ago
Engineering$251k–$375k/yrFull-time
Key Responsibilities
- Lead end-to-end physical design execution for complex multi-die switching products with UCIe and UALink connectivity
- Drive chip-level floorplanning, power planning, placement, routing, and timing closure for advanced node designs
- Establish physical design methodologies and best practices for interposer-based chiplet architectures and die-to-die interfaces
- Own physical design quality metrics including timing, power, area, and manufacturability across multiple concurrent projects
- Partner with architecture and digital design teams to influence RTL for physical implementation success
- Collaborate with packaging engineering on advanced 2.5D/3D integration strategies and interposer design
- Work closely with silicon engineering and DFT teams to ensure robust designs through tapeout and bring-up
- Drive resolution of critical timing, power, and signal integrity challenges in high-speed SerDes and switching fabrics
Basic Qualifications
- Bachelor's degree in Electrical Engineering, Computer Engineering, or related field
- 15+ years of experience in physical design and implementation of complex SoCs or ASICs
- Proven track record leading physical design teams and delivering multiple successful tapeouts in advanced process nodes (7nm or below)
- Deep expertise in chiplet architectures, interposer design, and die-to-die interface implementation
- Strong understanding of advanced packaging technologies including 2.5D and 3D integration
- Expert-level knowledge of physical design flows, timing closure, power optimization, and signoff methodologies
- Experience managing and scaling engineering teams of 20+ people
Preferred Qualifications
- Master's degree or PhD in Electrical Engineering or related field
- Experience with UCIe, PCIe Gen 6/7, or other high-speed SerDes physical implementation
- Background in AI/ML infrastructure, networking ASICs, or high-performance switching products
- Deep expertise with Cadence and/or Synopsys physical design tools and flows
- Experience with advanced DFT integration and design for manufacturability (DFM)
- Track record of innovation in physical design methodologies and automation
- Strong leadership and communication skills with ability to influence across organizations