Physical Design Engineer, ML4PD

We need to output HTML fragment with sections: About the role, Responsibilities, Requirements, Qualifications, Skills, Benefits, Pay, Schedule. Only include sections that have real specific content. Let's parse the posting. First paragraph: description of company, role: "Tenstorrent is leading the industry... We are growing our team and looking for contributors of all seniorities. Tenstorrent is looking for a mid- to senior-level Physical Design Engineer who will contribute to the physical design of high-performance chips for industry-leading AI/ML architectures, spanning implementation from synthesis through tapeout. You will partner with front-end and physical design engineers to optimize floorplanning, timing, power, performance, and area across multiple IPs. Along the way, you will build end-to-end ASIC expertise while learning from experienced engineers across the chip development process. This role is hybrid, based out of Austin, TX, Fort Collins, CO, or Santa Clara, CA. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting." That's about the role. Could be "About the role". Also includes location/hybrid. Next: "Who You Are" bullet points: engineer excited..., collaborative problem solver..., grounded..., curious... This could be "Qualifications" or "Skills"? It's more about desired traits. Could be "Qualifications". But we also have "What We Need" which lists education and experience: BS/MS/PhD, experience with synthesis, place-and-route flows, physical design tools, familiarity with timing, EM/IR, power analysis, ability to contribute across floorplanning, clocking, I/O planning, timing closure, area improvement, power optimization, strong Tcl, Perl, Shell, Python skills, knowledge of low-power techniques. That's "Requirements" or "Qualifications". Then "What You Will Learn" is learning outcomes: complete ASIC implementation lifecycle, how architecture influences physical implementation, how to develop flows and use experiments to optimize PPA, how to build physical design expertise while collaborating. That could be "Responsibilities"? Actually responsibilities are what you will do. The earlier part about partnering, optimizing floorplanning etc is responsibilities. The "What You Will Learn" is more about learning outcomes, could be under "Responsibilities" or maybe a separate section like "Learning Opportunities". But we only have set headings: About the role, Responsibilities, Requirements, Qualifications, Skills, Benefits, Pay, Schedule. We need to map content. We have compensation: "Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made. Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer." That gives Pay and Benefits. Benefits not detailed beyond "highly competitive compensation package and benefits". No specifics. Should we include Benefits section? The rule: include a section ONLY when the posting has real, specific content for it — never emit a heading followed by filler/placeholder text (e.g. "commensurate with experience", "not specified", "N/A", "varies", "TBD") and never create Pay/Schedule/Benefits sections unless the posting actually states them. Benefits: they say "highly competitive compensation package and benefits" but no specifics. That's vague; maybe considered filler? It's not specific benefits like health insurance, 401k, etc. So we should not create Benefits section unless there is specific content. Since they didn't list specific benefits, we should omit Benefits. Pay: they gave a range $100k - $500k including base and variable compensation targets. That's specific enough. So include Pay section. Schedule: they said hybrid role based out of locations. That's schedule? It's location/hybrid. Could be under Schedule? The posting says "This role is hybrid, based out of Austin, TX, Fort Collins, CO, or Santa Clara, CA." That's about work arrangement (hybrid). Could be considered Schedule? Usually schedule refers to full-time/part-time, hours. Hybrid is more about work location. But we have no explicit schedule like full-time. Might still include Schedule with hybrid info? The rule: include section only when posting has real, specific content for it. They gave hybrid and locations. That's specific. So we can include Schedule with that info. Now About the role: we can summarize the introductory paragraph about role and responsibilities? But we also have Responsibilities section for duties. Let's decide. About the role: maybe a brief overview: Tenstorrent is leading AI technology, looking for mid- to senior-level Physical Design Engineer to contribute to physical design of high-performance chips for AI/ML architectures, spanning synthesis through tapeout, partner with front-end and physical design engineers to optimize floorplanning, timing, power, performance, area across multiple IPs, build end-to-end ASIC expertise, hybrid role based in Austin, Fort Collins, Santa Clara. Responsibilities: list of duties: partner with front-end and physical design engineers to optimize floorplanning, timing, power, performance, and area across multiple IPs; build end-to-end ASIC expertise while learning from experienced engineers across chip development process; (maybe also) contribute to physical design of high-performance chips for industry-leading AI/ML architectures, spanning implementation from synthesis through tapeout. Actually that overlaps with About the role. We need to avoid duplication but preserve all substantive information. Could split: About the role includes company context and role purpose; Responsibilities includes specific tasks. Requirements: education and experience: BS/MS/PhD in EE, CE, CS or related field, strong logic design fundamentals; experience with synthesis, place-and-route flows, physical design tools; familiarity with timing, EM/IR, power analysis; ability to contribute across floorplanning, clocking, I/O planning, timing closure, area improvement, power optimization; strong Tcl, Perl, Shell, and/or Python skills; knowledge of low-power techniques such as power gating, multi-Vt, voltage scaling. Qualifications: maybe the "Who You Are" traits: engineer excited to work on high-performance designs for industry-leading AI/ML architectures; collaborative problem solver who enjoys working with experienced engineers across ASIC disciplines; grounded in logic design fundamentals and gate- and transistor-level implementation; curious about how early architectural and RTL decisions shape physical implementation and final chip quality. Skills: could be overlapping with Requirements; but we already have skills in Requirements. Maybe we can combine Requirements and Skills? But we need to follow headings only if content exists. Could put technical skills under Skills, and experience/education under Requirements. Let's decide. We have: Requirements: education + experience + tools. Skills: Tcl, Perl, Shell, Python, low-power techniques. But low-power techniques also in Requirements. Might duplicate. Better: Use Requirements for education/experience; Skills for technical skills (Tcl, Perl, Shell, Python, low-power techniques). Qualifications for personal traits. Let's extract. Education/Experience: BS, MS, or PhD in Electrical Engineering, Computer Engineering, Computer Science, or a related field, with strong logic design fundamentals. Experience with synthesis, place-and-route flows, and physical design tools, plus familiarity with timing, EM/IR, and power analysis. The ability to contribute across floorplanning, clocking, I/O planning, timing closure, area improvement, and power optimization. Skills: Strong Tcl, Perl, Shell, and/or Python skills, along with knowledge of low-power techniques such as power gating, multi-Vt, and voltage scaling. Qualifications (Who You Are): An engineer excited to work on high-performance designs for industry-leading AI/ML architectures. A collaborative problem solver who enjoys working with experienced engineers across ASIC disciplines. Grounded in logic design fundamentals and gate- and transistor-level implementation. Curious about how early architectural and RTL decisions shape physical implementation and final chip quality. Responsibilities: You will partner with front-end and physical design engineers to optimize floorplanning, timing, power, performance, and area across multiple IPs. Along the way, you will build end-to-end ASIC expertise while learning from experienced engineers across the chip development process. (Also maybe: contribute to the physical design of high-performance chips for industry-leading AI/ML architectures, spanning implementation from synthesis through tapeout.) But that is more about role. We'll include both. About the role: Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. Tenstorrent is looking for a mid- to senior-level Physical Design Engineer who will contribute to the physical design of high-performance chips for industry-leading AI/ML architectures, spanning implementation from synthesis through tapeout. You will partner with front-end and physical design engineers to optimize floorplanning, timing, power, performance, and area across multiple IPs. Along the way, you will build end-to-end ASIC expertise while learning from experienced engineers across the chip development process. This role is hybrid, based out of Austin, TX, Fort Collins, CO, or Santa Clara, CA. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. But note that some of that repeats responsibilities. Might be okay but we risk duplication. However instruction: Preserve ALL substantive information; do NOT invent or summarize away detail. So we need to keep all info, but we can avoid duplication by not repeating same sentences in multiple sections. We need to allocate each piece to a section uniquely. Let's list all distinct pieces: Company intro: Tenstorrent leading AI tech, revolutionizing performance, ease of use, cost efficiency. AI redefining computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, semiconductors. Diverse team developed high performance RISC-V CPU from scratch, share passion for AI, desire to build best AI platform. Value collaboration, curiosity, commitment to solving hard problems. Growing team, looking for contributors of all seniorities. Role description: Tenstorrent looking for mid- to senior-level Physical Design Engineer who will contribute to physical design of high-performance chips for industry-leading AI/ML architectures, spanning implementation from synthesis through tapeout. Work arrangement: This role is hybrid, based out of Austin, TX, Fort Collins, CO, or Santa Clara, CA. Experience level flexibility: We welcome candidates at various experience levels. During interview process, candidates will be assessed for appropriate level, offers align with that level, may differ from posting. Responsibilities: Partner with front-end and physical design engineers to optimize floorplanning, timing, power, performance, and area across multiple IPs. Build end-to-end ASIC expertise while learning from experienced engineers across chip development process. Learning outcomes (What You Will Learn): Complete ASIC implementation lifecycle, from synthesis through signoff and tapeout. How architecture, front-end design, and RTL decisions influence physical implementation outcomes. How to develop flows and use experiments to optimize power, performance, and area. How to build physical design expertise while collaborating with experts across advanced AI/ML silicon development. Who You Are traits: engineer excited to work on high-performance designs for industry-leading AI/ML architectures; collaborative problem solver who enjoys working with experienced engineers across ASIC disciplines; grounded in logic design fundamentals and gate- and transistor-level implementation; curious about how early architectural and RTL decisions shape physical implementation and final chip quality. Requirements (education/experience): BS, MS, or PhD in Electrical Engineering, Computer Engineering, Computer Science, or a related field, with strong logic design fundamentals. Experience with synthesis, place-and-route