PCIe, CXL and Highspeed IO Validation Engineer

At AMD, we believe technology can change lives for the better. It can heal us, entertain us, and make us more connected, productive, and understanding of the world around us. We’re looking for talent who want to leave the planet better than they found it—people who don’t shy away from humanity’s challenges but are determined to help solve them. AMD powers the next generation of supercomputing, high-performance computing, cloud, and AI. Every role at AMD contributes to technology that moves the world forward.

About the role

We are looking for a dynamic, energetic, and visionary principal validation engineer to join our growing datacenter CPU post-silicon validation team, specializing in high-speed IO such as PCI Express and Compute Express Link (CXL), multi-socket, and inter-die interfaces. As a key contributor, you will drive and improve AMD’s ability to deliver the highest quality, industry-leading technologies to market. The Systems Design Engineering and validation team fosters continuous technical innovation and career development.

Responsibilities

• Develop and execute feature enablement and validation test plans for SoC- and system-level features across all AMD Server products for High-Speed IO.
• Develop test content for both focus testing and system-level stress testing of the IO domain, plus cross-product stress testing.
• Develop post-silicon validation infrastructure (software, hardware, automation environment, and lab setup).
• Test interactions between various SoC features using validation infrastructure.
• Debug and drive root-cause analysis for SoC-related issues.
• Collaborate with cross-functional teams to develop tools that improve SoC validation and debug.
• Work with cross-functional teams to enhance post-silicon validation test strategy, methodology, and process.

Qualifications

• BSEE/CSE/CS with 7+ years of experience or MSEE/CSE/CS with 5+ years of experience.
• Proven hands-on experience in SoC design or validation of high-speed IO interfaces.
• Experience with PCIe Gen5/6+, CXL, UCIe, or proprietary inter-die and multi-socket server interfaces (electrical, functional, or both).
• Understanding of modern x86 microprocessor architecture and server platform architecture is highly desired.
• Experience developing validation methodologies and infrastructure.
• Test plan and workload development experience.
• Participation in silicon bring-up, debug, and support to internal engineering teams.
• Ability to execute and drive success of programs with multiple concurrent projects.
• Debug skills at both SoC and system level.
• Familiarity with programming/scripting languages (C/C++, Python, Perl, etc.).
• Working knowledge of server OSes (Linux, Windows).
• Self-starting team player with excellent communication skills who can work with minimal guidance.
• Forward thinker who drives improvements to development processes, code architecture, and fosters innovation.
• Strong verbal and written English communication skills.
• Extensive experience with common lab equipment (protocol/logic analyzers, oscilloscopes, etc.).
• Extensive experience with board/platform-level debug, including delivery, sequencing, analysis, and optimization.
• Strong knowledge of system architecture, technical debug, and validation strategy.
• Strong analytical and problem-solving skills with pronounced attention to detail.

Location

Austin, TX or Santa Clara, CA. This role is not eligible for visa sponsorship.

Benefits

AMD offers a comprehensive benefits package. AMD benefits at a glance.