PCIe, CXL and Highspeed IO Validation Engineer

Key Responsibilities

• Develop and execute feature enablement and validation test plans for SoC- and system-level SoC features across all AMD Server products for High-Speed IO
• Develop test content for both focus testing as well as system level stress testing of IO domain plus cross product stress testing
• Develop post-silicon validation infrastructure (software, hardware, automation environment, and lab setup)
• Test interactions between various SoC features using validation infrastructure
• Debug and drive root-cause analysis for SoC related issues
• Collaborate with cross-functional teams in developing tools to improve SoC validation and debug
• Work with cross-functional teams to improve post-silicon validation test strategy, methodology, and process

PREFERRED EXPERIENCE

• Proven hands on experience in soc design or validation of high speed IO interfaces
• Experience in PCIe Gen5/6+, CXL, UCIe or proprietary inter-die and multi-socket server interface in either electrical or functional or both
• Understanding of modern x86 microprocessor architecture and Server platform architecture is highly desired
• Experience developing validation methodologies and infrastructure
• Test plan and workload development experience
• Participated in silicon bring up and debug, support to internal engineering teams
• Able to execute and drive success of programs with multiple projects on the go
• Debug skills at both SoC and system level
• Familiarity with programming / scripting language (C/C++, Python, Perl, ...)
• Working knowledge of Server OSes (Linux, Windows)

ACADEMIC CREDENTIALS

• BSEE/CSE/CS with 7+ years of experience or MSEE/CSE/CS with 5+ years of experience