Package Mechanical FEA Engineer

Responsibilities

• Warpage and process simulation
• Predict warpage at each stage of the assembly process — bonding, reflow, underfill cure, encapsulation, lid attach, singulation — using process-sequential modeling rather than end-state analysis alone, including viscoelastic and cure-shrinkage behavior.
• Own the flatness, coplanarity, and facet planarity budgets that assembly and optical coupling depend on.
• Interconnect stress and reliability
• Analyze stress and strain in micro-bump, copper pillar, C4, and second-level interconnect structures, including chip-package interaction and low-k dielectric risk.
• Own solder and interconnect fatigue life prediction, and model thermal cycling, shock, drop, and board-level reliability against JEDEC and IPC methodology.
• Quantify stress in the photonic IC and its consequences for optical performance, in partnership with the photonic design team.

Qualifications

• MS or PhD in Mechanical Engineering, Materials Science, Engineering Mechanics, or equivalent practical background.
• 6+ years of structural FEA for semiconductor packaging, including warpage and interconnect stress analysis on a product carried into build.
• Deep hands-on capability in Ansys Mechanical, Abaqus, or equivalent, including nonlinear material modeling.
• Command of nonlinear and time-dependent material behavior — creep, viscoplasticity, viscoelasticity, fatigue — with correct treatment of temperature and rate dependence.
• Working knowledge of solder constitutive models and fatigue life prediction methods.
• Demonstrated correlation against physical measurement, and the judgment to distinguish a modeling error from a process excursion.