Package Design Engineer

Responsibilities

• Overall design responsibility for ASIC package designs, including aspects of signal integrity, power integrity, manufacturability, reliability, and thermal.
• Package Design of critical structures for SerDes, ADC/DAC, DDR, etc.
• Schedule, prioritize, & track your work across 2+ projects simultaneously
• General flip-chip BGA package design & engineering
• Project management and customer interface for your design projects
• Contribute to efficiency improvements for the design team, through process development/improvement, automation, documentation, etc.

Requirements

• BSEE or similar field and 12+ years’ experience in flip-chip-BGA package design, including high-speed SerDes
• MSEE or similar field and 10+ years’ work experience
• Knowledge of package-level signal integrity and power integrity, to apply to package designs
• Cadence APD (allegro package designer) experience is preferred. Equivalent tool is OK.
• Cooperate with our world-wide team (multiple time zones), including co-design with internal team members and external (Vendor) designers
• Self-management and organization skills

Education/Experience & Requirements

Preferred candidates will also have 1 or more years experience with Cadence SKILL for Allegro, or similar design-automation coding experience and interest.

Other Requirements

This job requires working on-site at the Broadcom office, 5 days a week. This is not a remote-work position.

Pay & Benefits

Pay: The annual base salary range for this position is $141,300 - $226,000.

Benefits: Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time. The company follows all applicable laws for Paid Family Leave and other leaves of absence.