MTS - HIG HBM - ARCHITECTURE

Our vision is to transform how the world uses information to enrich life for all. Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. The High‑Performance Integrated Group (HIG) within the Technology and Products Group (TPG) is dedicated to developing and optimizing High Bandwidth Memory (HBM) solutions for AI and ML applications, with the ultimate goal of delivering the lowest power‑per‑bit solutions in the industry.

Position Overview

We are searching for an HBM IO Design Architecture Engineer to build and own the end‑to‑end design quality system — including design checklist delivery, silicon data analysis, and cross‑team data collection framework — ensuring that silicon learnings are systematically captured and fed back into the project before the next generation design is finalized. The ideal candidate brings hands‑on experience in design execution, simulation‑to‑silicon correlation, and cross‑functional methodology development, and embraces AI‑driven analysis and data‑driven decision making to accelerate quality improvement cycles.

Responsibilities

• High‑speed IO design architecture for HBM products.
• Define and standardize IO design quality process from architecture to silicon.
• Work with Product Engineering to correlate silicon measurements and simulation performance for circuit‑level design analysis.
• Contribute to cross‑group communication to work towards standardization and group success.
• Proactively solicit input from Standards, CAD, modeling, and verification groups to ensure design quality.
• Drive innovation into future memory generations in a multifaceted work environment.
• Leverage AI‑assisted analytics to accelerate root‑cause identification from complex multi‑variable silicon data.

Qualifications

• Prior industrial experience in high‑speed clocking design at 32 Gbps+ speed.
• Strong IO circuit design background with familiarity in both analog and digital design; simulation experience required.
• Experience with circuit verification and optimization, including layout verification and parasitic extraction.
• Familiarity with one or more off‑chip protocols such as UCIe, HBM, DDR, PCIe, MIPI, etc.
• Good understanding of state‑of‑the‑art device characteristics and hands‑on design experience.
• Excellent problem‑solving, analytical, and documentation skills.
• Strong communication skills, both verbal and written, to convey sophisticated technical concepts.
• Prior circuit debug experience through Product Engineering or equivalent preferred.
• Knowledge of advanced packaging environments (CoWoS, HBM stack, D2D, etc.).
• MS or PhD in Electrical Engineering.
• 10+ years of relevant engineering or design experience on high‑speed IO, PLL, Tx, Rx, equalization, clock tree.
• Job title and level can scale depending on experience and qualifications.

Benefits

Micron offers a comprehensive benefits program designed to support personal wellbeing and professional growth, including a choice of medical, dental, and vision plans; income‑protection programs for illness or injury; paid family leave; a robust paid time‑off program; and paid holidays. Additional details are available in the Benefits Guide on micron.com/careers/benefits.