Mixed-Signal Design Verification Engineer | Custom

About the role

Join our Top-Level Design Verification (TLDV) Team in the ACS product line, developing cutting-edge ASSP ICs. The TLDV team builds automated AMS and DMS testbenches to verify logical functionality, electrical parameters, performance, and reliability of custom high-volume chips. We focus on continuous improvement in tools and methodologies, teamwork, and collaboration.

Responsibilities

• Execute pre-silicon verification of complex mixed-signal IC products.
• Build scalable testbench and automation solutions supporting DMS and AMS stimulus and checkers to verify DUT behavior before tapeout.
• Verify high-speed clock and data paths (clock/data recovery, timing, serialization/de-serialization, PLLs, DLLs) such as USB, eUSB, SerDes, and other wireline protocols.
• Verify designs to meet datasheet, VVCM, system-level use cases, design-for-test features, and usability from customer and bench/ATE perspectives.
• Collaborate with design and systems teams to guide Design for Verification architecture, triage and close bugs, and clarify datasheet and VVCM specifications.
• Use languages and tools such as Verilog, SystemVerilog, Verilog-AMS, Cadence Virtuoso, Spectre, Simvision, scripting languages, Starfish, CDDS, functional coverage, RTL code coverage, and constrained-random stimulus.
• Evaluate and recreate system-level use-cases in simulation, including customer communication to understand these cases and review results.
• Create and maintain behavioral models of analog circuits (real-number models, simple logical models, Verilog-AMS electrical or wreal models, or simple schematic models).

Requirements

• 8+ years of experience as a Design Verification Engineer, including 4+ years of design verification of high-speed clock/data paths (e.g., USB, SerDes, PLL, DLL).
• Strong understanding of mixed-signal and digital verification flows (AMS / DMS / TLDV / DDV) and modeling of analog blocks.
• Solid analog design knowledge with the ability to understand and explain operation at the schematic level, including effects of PVT and layout parasitics.
• Solid digital design knowledge with the ability to understand RTL, FSMs, GLS, timing, synchronization, power domains, and clock domains.
• Experience in verification of timing with Gates+SDF, electrical PVT variation, and timing across analog and digital boundaries.
• Experience creating and maintaining tools and scripts for automation related to design, verification, simulation, data collection, and analysis.
• Excellent debug skills with high attention to detail for both analog and digital behaviors.
• Strong leadership, communication, cross-team collaboration, and customer-facing skills.
• Strong analytical and problem-solving skills.
• Ability to work in a fast-paced and rapidly changing environment.

Preferred Qualifications

• Experience verifying USB protocol (USB2.0 and eUSB, high-speed and full-speed, logical and electrical).
• Experience in modeling analog blocks as real-number models using SystemVerilog.
• Experience verifying re-timers, re-drivers, SerDes.
• Experience with Verification IPs (VIPs) for USB, eUSB, PLLs, or other SerDes interfaces.

About Us

At Texas Instruments, we empower our employees to own their career and development. Collaborate with some of the smartest people in the world to shape the future of electronics. We value diverse backgrounds and perspectives, which drive innovation and strengthen our team.

Benefits

We offer competitive pay and benefits designed to support you and your family. Your well-being is important to us. For country-specific benefits, visit our benefits page.