Member of Technical Staff, ASIC Architecture

Responsibilities

• Performance modeling for GPU memory subsystems and memory-semantics interconnects
• Architecting data and control planes for high-speed data movement
• Designing and simulating I/O-heavy SoC architectures
• Possess SoC and system architecture specs from inception through high-volume production
• Partner with silicon and software teams to ensure implementation aligns with architecture specs

Qualifications

• BS/MS or PhD in Electrical Engineering or Computer Science with 5+ years of relevant experience
• Strong background in computer architecture with a focus on memory systems and memory-semantics interconnects
• Strong understanding of scale-up memory fabric and protocols
• Familiarity with GPU memory organization
• Experience running detailed performance modeling for computing and/or data movement ASICs
• Familiarity with state-of-the-art distributed ML algorithms

Preferred Qualifications

• Experience architecting endpoints for memory-semantics interconnects: CXL, NVLink, UALink, RDMA
• Experience building AI accelerators
• Background in cloud virtualization and hardware security
• Knowledge of ARM CHI / UCIe