Member of Technical Staff, AI‑Optimized Memory Digital Design Engineer / Microarchitect

Our vision is to transform how the world uses information to enrich life for all. Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Join our team where we are building next-generation, high-performance memory solutions for AI.

About the role

In Micron's AI-optimized Memory Architecture organization, we partner closely with customers to design and deliver memory solutions purpose-built for emerging AI systems and applications. As a Member of Technical Staff in the AI-optimized Architecture team, you will contribute to the microarchitecture and design of tightly coupled, high-performance memory for AI. Apply expert knowledge to realize architecture features into silicon, with a strong focus on performance, power, area (PPA), and reliability. This role is ideal for an engineer who combines deep digital design experience with strong architecture intuition, motivated by turning architectural intent into efficient, silicon-proven implementations.

Responsibilities

• Translate architecture requirements into efficient, scalable microarchitectures that optimize systems metrics with ownership from concept through implementation.
• Design, implement, and review SystemVerilog designs for memory systems architectures.
• Perform synthesis and early analysis to estimate and optimize area, power, and timing, and to guide architecture and microarchitecture tradeoffs.
• Compose and maintain clear microarchitecture documentation that aligns design intent across teams.
• Drive technical decisions by evaluating tradeoffs across microarchitecture and implementation constraints.

Requirements

• Strong experience in digital design and microarchitecture development, including ownership of hardware blocks from specification through implementation.
• Solid understanding of computer and memory system architecture with an ability to reason about SoC-level behavior and tradeoffs.
• Experience with synthesis, and early PPA estimation and optimization.
• Experience in one or more high-level programming languages (e.g., C/C++, Python) and hardware description languages (e.g., SystemVerilog).
• Ability to influence others through deeply technical, data-driven analysis.

Qualifications

• Familiarity with memory interfaces and memory systems concepts (reliability, media management, etc.).
• Experience connecting architecture and implementation by influencing architecture features with a clear understanding of RTL cost and feasibility.
• A Masters or PhD in Computer Science, Computer Engineering, Electrical Engineering, or equivalent experience.
• 5+ years of proven industry experience delivering silicon-demonstrated memory systems and SoC hardware designs on modern foundry nodes.

Pay

The US base salary range for this full-time position is $177,000.00 - $309,000.00 a year. Additional compensation may include benefits, bonuses, and equity. Salary ranges are determined by role, level, and location, with individual pay based on work location and job-related factors such as knowledge, skills, experience, tenure, and relevant education or training.

Benefits

• A choice of medical, dental, and vision plans.
• Income protection programs if unable to work due to illness or injury, and paid family leave.
• A robust paid time-off program and paid holidays.