Low Power ASIC Engineer - New College Grad 2026

About the role

We are seeking a Low Power Design/Verification ASIC Engineer - New College Grad 2026 to join our Low Power DV team. This role involves working closely with Low Power Architecture, Design, and Software teams to understand next-generation features. You will architect, develop testbenches, infrastructure, and test plans to verify various power management solutions for NVIDIA products. Additionally, you will contribute to improving power-aware DV methodologies and influencing EDA vendor improvements in simulation and debug efficiencies.

Responsibilities

• Work closely with Low Power Architecture, Design, and Software teams to understand next generation features.
• Architect, develop testbenches, infrastructure, and test plans to verify various power management solutions for NVIDIA products.
• Influence EDA vendors to improve simulation and debug efficiencies.
• Become involved in developing state-of-the-art GPUs for AI, Automotive, GeForce, and Mobile products.

Requirements

• Recently completed a BS, MS, or PhD in Electrical or Computer Engineering, or equivalent experience.
• Understanding of low power design techniques such as multi VT, clock gating, power gating, block activity power, and dynamic voltage-frequency scaling (DVFS).
• Good understanding of processor architecture (GPU is a plus), and related power management design/DV techniques.
• Experienced with Incisive Low-Power or Synopsys VCS NLP.
• Strong debug skills and experience with Verdi.
• Fluent in Verilog, SystemVerilog, and understanding of UVM.

Qualifications

• Prior knowledge of Low Power Architecture, Low Power CV, and deep learning.
• Good understanding of power intent in UPF format.
• A strong background in Low Power architectures or verification.
• Scripting abilities in Python or Perl.
• Knowledge of C or C++.
• Experience writing or maintaining scripts or Makefiles that build the simulation program.

Skills

• Verilog, SystemVerilog, UVM.
• Debug skills, Verdi.
• Power management design/DV techniques.
• EDA vendor simulation and debug efficiency improvements.
• Low Power Architecture, Low Power CV, Deep Learning.
• UPF format power intent understanding.
• Low Power architectures or verification background.
• Python or Perl scripting.
• C or C++ knowledge.
• Experience with scripts or Makefiles for simulation programs.

Benefits

NVIDIA offers competitive compensation packages including base salaries ranging from $100,000 to $166,750 for Level 1 and $116,000 to $189,750 for Level 2, along with equity and benefits. Applications are open until June 6, 2026.

Pay

Base salary range: $100,000 - $166,750 for Level 1, and $116,000 - $189,750 for Level 2.

Schedule

Full-time position.

Company Information

NVIDIA is committed to fostering an inclusive work environment and is an equal opportunity employer. We highly value diversity in our workforce and do not discriminate on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status, or any other characteristic protected by law.