Logic Design Engineer

About the role

Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the team behind Microsoft’s expanding Cloud Infrastructure and responsible for powering Microsoft’s “Intelligent Cloud” mission. SCHIE delivers the core infrastructure and foundational technologies for Microsoft's over 200 online businesses including Bing, MSN, Office 365, Xbox Live, Teams, OneDrive, and the Microsoft Azure platform globally with our server and data center infrastructure, security and compliance, operations, globalization, and manageability solutions. Our focus is on smart growth, high efficiency, and delivering a trusted experience to customers and partners worldwide.

The Compute Silicon & Manufacturing Engineering (CSME) organization within SCHIE is responsible for design, development, manufacturing and packaging of Microsoft's state-of-the-art computer chips, notably the Azure Cobalt. Our solutions provide sustainable strategic advantages to Microsoft and enable our customers to achieve more. As Microsoft's cloud business continues to grow the ability to deploy new offerings and hardware infrastructure on time, in high volume with high quality and lowest cost is of paramount importance. To achieve this goal, the CSME organization is instrumental in defining and delivering operational measures of success for hardware manufacturing, improving the planning process, quality, delivery, scale and sustainability related to Microsoft cloud hardware.

We are looking for a Logic Design Engineer to join the team to support our mission and culture. This key role will impact the organization by contributing to the microarchitecture and logic design of clock controllers.

Responsibilities

• Development and Integration of various functional block RTL related to SOC clock controllers
• Perform design quality checks such as Timing closure, Lint, CDC, Synthesis, Low Power Intent
• Utilize AI for gaining efficiency within process and development
• Interface with verification team to ensure functional correctness
• Interface with physical design, design-for-test, and other teams to deliver qualified physical partitions evaluating tradeoffs and delivering high quality design
• Exercise the functionality of the block by writing basic tests and debug for various features at IP and SoC levels as deemed necessary
• Automate tasks using scripting for efficiency
• Delight your customers by providing high quality functional blocks on schedule and with professional integrity
• Challenge the status quo with growth mindset

Qualifications

Required Qualifications:

• Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 1+ year(s) technical engineering experience
• OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 2+ years technical engineering experience
• OR equivalent experience

Preferred Qualifications:

• Minimum 2+ year logic design experience
• Knowledge of logic design flow including Low Power Analysis, UPF, RTL coding, Synthesis, timing constraints, timing closure
• 2+ years of experience designing clock controller IP
• Proficient in Verilog/System Verilog coding constructs
• Knowledge of front-end tools (VCLP, Verilog simulators, Connectivity tools, low power static checkers, linting)
• Demonstrated experience and knowledge of clock crossings, and power/UPF in design
• Familiarity with Industry standard interface protocols (ARM) is a plus
• Familiarity with Formal Equivalence Verification and Power Analysis is a plus
• Good verbal and written communication skills

Security Requirements

• Ability to meet Microsoft, customer and/or government security screening requirements
• Microsoft Cloud Background Check: required upon hire/transfer and every two years thereafter
• Citizenship & Citizenship Verification: role requires access to export-controlled information under U.S. ITAR/EAR, EU Dual Use Regulation, and/or other export control regulations
• As a condition of employment, the successful candidate must provide proof of country of citizenship or proof of U.S. permanent residency or other protected status (e.g., under 8 U.S.C. 1324b(a)(3)) for assessment of eligibility to access export-controlled information
• Citizenship will be verified with a valid passport; lawful permanent residents, refugees, and asylees may verify status using other documents where applicable

Pay

Silicon Engineering IC3 — The typical base pay range for this role across the U.S. is USD $102,100 - $202,200 per year. For specific work locations within the San Francisco Bay area and New York City metropolitan area, the base pay range is USD $133,800 - $219,200 per year. Certain roles may be eligible for benefits and other compensation.