Lead DFT Engineer
Saur Energy International · Location, WV · 3 wk ago
Full-time
About the role
Digital Design Engineer with hands‑on experience in scan insertion, ATPG, and GLS.
Responsibilities
- Understand the DFT architecture of the design and provide scan insertion collaterals to the implementation team to enable scan insertion flows during synthesis.
Requirements
- Proficiency in industry‑standard DFT tools such as Mentor Tessent, Synopsys DFT Compiler, Cadence Encounter Test.
- Ability to contribute to ATPG at partition and SoC level.
- Experience with DFT GLS simulation tools and methodologies, including fault modeling and coverage analysis.
- Familiarity with industry standards such as IEEE 1149.1 (JTAG) and IEEE 1687 (IJTAG).
- Effective communication and teamwork skills, with the ability to collaborate across functions.