Lead Design Verification Application Engineer

About the role

The ideal candidate will be energetic, innovative, and enthusiastic about helping customers solve their toughest verification problems using Cadence technology. This role involves working closely with industry-leading semiconductor and system companies to deploy Cadence’s market-leading verification platforms, including cutting-edge technologies like AI assistants and machine learning.

Responsibilities

• Work directly with industry leading semiconductor and system companies to deploy Cadence’s market leading verification platforms
• Provide the front-line technical support in the pre and post-sales process
• Develop customer-specific verification requirements, including advanced verification component development, methodology support, and operation and maintenance of Cadence’s verification tools and services
• Support technical evaluations and benchmark development for Cadence’s market leading tools such as Xcelium simulation platform and Verisium platform of AI and ML tools for enhanced verification
• Create and conduct technical presentations and product demonstrations for customers
• Champion the customer needs and work with R&D and marketing to develop competitive and creative technical solutions
• Write technical product literature such as application notes and technical articles

Requirements

• Minimum: BS, MS, or PhD degree in Computer Science/Engineering, Electrical Engineering, or related field
• 3+ years experience with SystemVerilog, VHDL, Verilog
• Good understanding and knowledge of Object Oriented Programming and experience in one such programming language such as C++, Java, Python or SystemVerilog
• Strong verbal and written communication skills
• Self-motivated and strong teamwork skills
• Strong problem-solving skills

Preferred Experience

• Experience with simulation, functional verification, testbench creation and debug
• Education or experience in Verilog/SystemVerilog
• Knowledge of design fundamentals such as architecture, micro-architecture, HDLs and Synthesis and timing
• Digital design or digital verification experience

Benefits

• Annual salary range for California: $102,900 to $191,100
• On Target Earnings (OTE) incentive compensation structure
• Paid vacation and paid holidays
• 401(k) plan with employer match
• Employee stock purchase plan
• A variety of medical, dental and vision plan options