Lead ASIC Design Engineer, Amazon Leo

Key job responsibilities

Lead RTL design and development of large subsystems and custom blocks. Integrate IP cores by choosing configuration and connectivity options to fit system requirements. Assimilate IP collateral to become the team's expert.

Ownership as cognizant designer for integration with software. Partner with verification team to ensure complete test plans and functional coverage. Support the design through all phases: RTL/Gate simulations, emulation and post silicon implementations.

In this role you will:

• Work closely with the system architects to develop world-class SOC and IP blocks, which meet power, area and performance targets.
• Lead the definition, configuration and integration of SoC Subsystems of various types: Ethernet, SERDES, LPDDR5/6X, Arm CPU
• Configure and integrate 3rd party IP blocks, develop support logic
• Contribute to the SoC floor planning effort
• Understand low power design & the impact of DFT on the blocks
• Perform initial synthesis, timing analysis, CDC analysis and other back end interface flows
• Assist verification team in unit verification including test plan development
• Aid debug and bring-up

Basic Qualifications

• 8+ years of ASIC implementation, synthesis, STA and physical design in deep sub-micron nodes (16nm or smaller) experience
• 8+ years of digital design in communication systems experience
• 8+ years of wireless communications systems and implementation experience
• Bachelor's degree in Electrical Engineering or a related field
• Bachelor's degree in Electrical Engineering/Communications Engineering, or experience designing digital communication systems
• Knowledge of implementing chips with multiple power islands and power gating
• Knowledge of serial protocols including SPI, I2C, I3C, and UART
• Experience low power design techniques

Preferred Qualifications

• Master's degree or Ph.D. degree in Electrical Engineering or related field
• Experience with modern ASIC/FPGA design and verification tools
• Experience with SOC bring-up and post-silicon validation