Lead Analog IC Layout Engineer
Analog Devices · Wilmington, MA · 3 wk ago
Engineering$135k–$202k/yrFull-time
About the ATE Group
The Automatic Test Equipment (ATE) organization within Instrumentation delivers high-performance solutions that enable production testing of advanced electrical and electronic systems—from high-speed microprocessors to high-voltage EV battery modules. We partner closely with customers to define cutting-edge stimulus and measurement architectures, driving improvements in accuracy, energy efficiency, test time, and channel density to provide differentiated ATE capability.
Key Responsibilities
- Own the layout of complex blocks, including scheduling, floor planning, verification, and tapeout
- Develops solutions to complex problems requiring specialized expertise and in-depth analysis
- Acts as a primary technical resource for less experienced engineers
- Leads teams and complex projects with substantial business impact
- Influences across organizational boundaries to drive technical excellence
- Leads complex IC layout projects and mentors junior engineers
- Makes critical IC architecture design decisions that shape product development
- Performs advanced process evaluations and optimizations
- Develops layout methodologies and best practices that enhance team productivity and results
Must Have Skills
- Technical Leadership: Advanced technical expertise with recognized influence in the organization
- Expert-Level Design Skills: Expert-level proficiency in IC layout, architecture design, and process evaluation
- Collaboration: Capability to work with global teams and support creative and collaborative environments
- Process Innovation: Capability to develop and implement innovative layout methodologies that advance organizational capabilities
Preferred Education And Experience
- Bachelor's degree in Electrical/Computer Engineering or related field, or equivalent experience
- 7+ years of relevant experience
- Proficiency with Cadence Virtuoso, including strong VXL expertise
- Strong understanding of LVS, DRC, antenna checks, and associated verification/debug methodologies