Intern - PHY Digital Design & Automation Engineer, HBM

About the role

Micron Technology’s Heterogeneous Integration Group (HIG) HBM Architecture team develops future High‑Bandwidth Memory (HBM) architectures, PHY design methodologies, and automation solutions for next‑generation AI, high‑performance computing, networking, and data‑center applications. The team collaborates closely with Architecture, Design Engineering, Verification, Product Engineering, and external partners to advance memory technologies while improving design quality, productivity, and development efficiency.

As a Senior or Graduate Engineering Intern, you will work with experienced HBM architects and engineers to support the development of digital design methodologies, automation frameworks, timing analysis flows, and architecture validation solutions for next‑generation HBM PHY and I/O subsystems. The role provides hands‑on experience in digital design, verification, automation, and timing analysis, and offers opportunities to leverage AI‑assisted engineering workflows, Large Language Models (LLMs), and Generative AI tools to enhance productivity and design efficiency.

Responsibilities

• Support digital design, integration, and timing analysis activities for HBM PHY and I/O subsystems, including timing constraint development and timing‑closure efforts.
• Develop and implement verification solutions using Verilog/SystemVerilog and UVM‑based environments; analyze simulation results and debug functional or timing‑related issues.
• Create Python‑based automation tools and AI‑assisted engineering workflows that leverage Large Language Models (LLMs) and Generative AI technologies to improve engineering efficiency.
• Collaborate with architecture, design, verification, and product‑engineering teams to evaluate features, validate architectures, and improve design‑quality metrics.
• Document technical findings and present results through design reviews, engineering discussions, and project presentations.

Minimum Qualifications

• Currently pursuing a Master’s or Ph.D. degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field.
• Understanding of digital design concepts including finite‑state machines (FSMs), pipelining, clock‑domain crossing (CDC), timing analysis, and computer architecture.
• Experience with RTL design and verification concepts using Verilog or SystemVerilog.
• Proficiency in Python, C++, or a comparable programming language, and experience working in Linux‑based development environments.
• Strong analytical, debugging, problem‑solving, written communication, and verbal communication skills.

Preferred Qualifications

• Experience with digital implementation flows, static timing analysis (STA), timing‑closure methodologies, and timing‑constraint development.
• Familiarity with UVM‑based verification environments and regression‑infrastructure development.
• Experience using EDA tools from Cadence, Synopsys, Siemens, or equivalent vendors.
• Exposure to automation, software development, data analytics, AI‑assisted workflows, Large Language Models (LLMs), or Generative AI‑based productivity solutions.
• Coursework, research, or project experience related to VLSI design, digital systems, computer architecture, memory systems, timing analysis, or mixed‑signal design environments.

Benefits

• Choice of medical, dental, and vision plans at all locations, allowing team members to select coverage that best meets family healthcare needs and budget.
• Benefit programs that protect income if unable to work due to illness or injury.
• Paid family leave.
• Robust paid time‑off program and paid holidays.
• Additional details available in the Benefits Guide posted on micron.com/careers/benefits.