Intern - Characterization and Support (Fall 2026)

About the role

This is an on-site internship role in San Jose, California, within the Cadence DDR IP group for a Post-Silicon Validation Engineering Intern. Local candidates will be considered.

Responsibilities

• Validate both system-level and electrical performance of internal silicon test chips.
• Debug silicon issues in close collaboration with analog and digital design teams.
• Deliver high-quality characterization reports.
• Work cross-functionally to ensure product functionality, reliability, and successful deployment.

Requirements

• Currently pursuing a Bachelor's or Master’s degree in electrical engineering with 0–2 years of relevant work experience.
• Very good fundamentals in analog and digital electronics, RTL, signal integrity, and control systems.
• Strong analytical and problem-solving skills.
• Excellent written and verbal communication skills.
• Ability to work collaboratively in a team environment.
• Prior experience in the hardware semiconductor or electronics industry is a plus.
• Experience with script-based test automation in Python, C, or other scripting tools is a plus.
• Applicants should ideally be attending a local school and able to work full-time hours in San Jose during the Fall semester.
• Must have legal authorization to work in the US.

Pay

The annual salary range for California is $40/hr to $69/hr. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. The salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies, and work location.