Intern - Characterization and Support
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. This is an on-site internship role in San Jose, California, within the Cadence DDR IP group.
About the role
As a Post-Silicon Validation Engineering Intern, you will be responsible for validating both system-level and electrical performance of internal silicon test chips. The role includes debugging silicon issues in close collaboration with analog and digital design teams, and delivering high-quality characterization reports. You will work cross-functionally to ensure product functionality, reliability, and successful deployment.
The candidate is expected to be strongly motivated by the prospect of driving system and electrical testing efforts for identifying silicon issues and being involved in debug efforts for the same.
Requirements
- Currently pursuing a Bachelor's or Master’s degree in electrical engineering with 0-2 years of relevant work experience
- Very good fundamentals in analog and digital electronics, RTL, signal integrity, and control systems
- Strong analytical and problem-solving skills
- Excellent written and verbal communication skills
- Ability to work collaboratively in a team environment
- Prior experience in the hardware semiconductor or electronics industry is a plus
- Experience with script-based test automation in Python, C, or other scripting tools is a plus
- As this role is expected to be employed in San Jose during the Fall semester, applicants should ideally be attending a local school
Pay
The annual salary range for California is $40/hr to $69/hr. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. The salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies, and work location.