HSIO Validation Lead – Silicon Co-Design

About the role

The Silicon Co-Design Group at NVIDIA leads the boundary between what was designed and what was built. You will own the full stack—from protocol behavior and signal integrity to firmware, platform topology, and silicon marginalities—ensuring high-speed interfaces like PCIe, NVLink, and C2C work reliably at scale. Your work directly impacts yield, production ramp, and field quality, shaping how NVIDIA validates interfaces across generations.

Responsibilities

• Own post-silicon bring-up, characterization, validation, and debug of PCIe, NVLink, C2C, and other high-speed I/O (HSIO) interfaces across NVIDIA GPUs, CPUs, and SoCs from first power-on through production readiness.
• Drive root cause analysis and resolution for the hardest failures, spanning protocol behavior, signal integrity, firmware/driver interactions, platform topology, and silicon marginalities. Own fixes through confirmation.
• Define validation strategy, including test coverage, debug priorities, margining methodology, and stress criteria for each program to prevent customer escapes.
• Develop and deploy AI agents (e.g., automated debug triage, intelligent data pipelines) to reduce cycle time and identify issues pre-production. Balance AI acceleration with risk mitigation.
• Ensure robust interoperability across the ecosystem: retimers, switches, accelerators, CPUs, GPUs, and multi-device system topologies.
• Drive cross-functional alignment with architecture, logic design, circuit design, firmware, drivers, ATE, DGX, and product teams. Your data settles critical decisions.
• Translate lessons from real silicon into methodology and coverage improvements for future products.

Requirements

• BS or MS in Electrical Engineering, Computer Engineering, Systems Engineering, or equivalent lab experience.
• 8+ years in silicon validation, HSIO bring-up, or high-speed interface debug on real hardware.
• Deep protocol expertise in PCIe, NVLink, CXL, C2C, Ethernet, USB, or similar high-speed interfaces.
• Strong signal integrity fundamentals: SERDES behavior, link training, equalization, clocking, reset, power management, and high-speed board/system interactions.
• Hands-on lab experience with oscilloscopes, BERTs, protocol analyzers, logic analyzers, exercisers, and silicon debug tools.
• Ability to debug across hardware, firmware, drivers, and platform design without losing the thread.
• Statistical proficiency to interpret marginal distributions and intuition to guide next steps.

Skills

• Recognized depth in PCIe, NVLink, CXL, or advanced SERDES validation, with a track record of solving failures others couldn’t.
• Experience building or deploying AI-driven flows for HSIO debug or failure triage, with clear outcomes and guardrails.
• Proven ability to resolve customer-critical or production-blocking HSIO failures under schedule pressure.
• Experience setting technical direction for validation teams or mentoring engineers into subsystem experts.

Pay

Base salary ranges: $168,000–$264,500 (Level 4) or $196,000–$310,500 (Level 5), determined by location, experience, and internal benchmarks. Eligible for equity and benefits.