HSIO Validation Lead – Silicon Co-Design

About the role

The Silicon Co-Design Group leads the boundary between what was designed and what was built. When a GPU, CPU, or SoC ships with interfaces that work at scale, this team is the reason. Most engineers debug within a layer. You will own the full stack.

Responsibilities

• Own post-silicon bring-up, characterization, validation, and debug of PCIe, NVLink, C2C, and other HSIO interfaces across NVIDIA GPUs, CPUs, and SoCs from first power-on through production readiness.
• Close the hardest failures. Drive root cause across protocol behavior, signal integrity, firmware and driver interactions, platform topology, and silicon marginalities and own every fix through to confirmation.
• Define validation strategy. Set test coverage, debug priorities, margining methodology, and stress criteria for each program. Your strategy is what stands between a silicon risk and a customer escape.
• Own and build AI agents that operate under your direction. These include automated debug triage, intelligent data pipelines, and analysis flows. They reduce cycle time and identify issues before production.
• Ensure robust interoperability across the full ecosystem: retimers, switches, accelerators, CPUs, GPUs, and sophisticated multi-device system topologies.
• Sit at the decision table. Your analysis drives alignment across architecture, logic design, circuit design, firmware, drivers, ATE, DGX, and product teams. Your data is what settles calls.
• Translate what you learn on real silicon into methodology and coverage improvements that make future products harder to escape.

Requirements

• BS or MS in Electrical Engineering, Computer Engineering, or Systems Engineering, or equivalent experience in the lab.
• 8+ years in silicon validation, HSIO bring-up, or high-speed interface debug on real hardware.
• Deep protocol expertise in PCIe, NVLink, CXL, C2C, Ethernet, USB, or similar high-speed interface technologies.
• Strong signal integrity fundamentals: SERDES behavior, link training, equalization, clocking, reset, power management, and high-speed board and system interactions.
• Hands-on lab depth: oscilloscopes, BERTs, protocol analyzers, logic analyzers, exercisers, and silicon debug tools.
• The ability to debug across the full stack, hardware, firmware, drivers, and platform design, without losing the thread.
• Moderate statistical proficiency to recognize the moments a marginal distribution is telling you something and enough develop intuition to know where to look next!

Qualifications

• Recognized depth in PCIe, NVLink, CXL, or advanced SERDES validation, with failures that other teams brought to you.
• Experience building or deploying AI-driven flows for HSIO debug or failure triage, and can speak to both the outcome and the guardrails.
• Track record of solving customer-critical or production-blocking HSIO failures under schedule pressure and driving them all the way through.
• Experience setting technical direction across a validation organization or developing engineers into recognized subsystem experts.

Skills

• Deep understanding of high-speed serial interfaces like PCIe, NVLink, CXL, and C2C.
• Strong debugging skills across multiple layers of the stack.
• Ability to define and execute comprehensive validation strategies.
• Experience with AI-driven debug and triage tools.
• Excellent communication and collaboration skills to influence cross-functional teams.

Benefits

• Competitive base salary ranging from $168,000 to $264,500 for Level 4, and $196,000 to $310,500 for Level 5.
• Equity and benefits package.

Pay

Your base salary will be determined based on your location, experience, and the pay of employees in similar positions.

Schedule

Full-time position.