Hardware Verification Engineer (TERADYNE, Agoura Hills, CA)

About the Role

Teradyne’s Silicon Technology Engineering (STE) group is seeking a senior engineering leader to lead the bench characterization team supporting new product development. This role combines people leadership with hands-on technical guidance, with an expected focus of approximately 70% leadership and 30% technical contribution. The position partners closely with ASIC design, ATE test, program/product management, and internal customers to deliver characterization results that support project goals.

Responsibilities

• Lead, coach, and develop a team of characterization engineers, including onboarding, feedback, prioritization, and career development.
• Partner with program/product management, ASIC design, ATE test, and internal customers to translate requirements into clear characterization execution plans.
• Guide bench-level test plans, PCB interface considerations, DUT communication, and automated measurement approaches.
• Review characterization data, correlate findings to system-level parameters, and ensure reports are ready for stakeholder review.
• Support complex bench-level debug, failure analysis, and failure-isolation activities.
• Communicate team progress, risks, and priorities to engineering leadership.

Requirements

• Bachelor’s degree in Engineering or Physics required; Electrical/Computer Engineering preferred.
• 10+ years of related work experience preferred in semiconductor characterization, bench measurements, mixed-signal systems, or related engineering work.
• Experience leading, mentoring, or managing engineers, or demonstrated readiness to grow into people leadership.
• Experience using benchtop equipment such as power supplies, SMUs, semiconductor parameter analyzers, multimeters, signal generators, AWGs, pattern generators, BERTs, oscilloscopes, VNAs, and spectrum analyzers.
• Programming experience; VBA (Visual Basic for Applications) preferred, with additional knowledge of Python, MATLAB, or C++ a plus.
• Experience programming in Verilog and working with SCPI communication.
• Experience with mixed-signal (analog and digital) systems, multi-GHz signal delivery, de-embedding, and signal/power integrity preferred.
• Experience characterizing PLLs, jitter, data eyes, DACs, and ADCs preferred.
• Experience with revision control; Git preferred.
• Strong cross-functional communication skills and the ability to represent the team to senior stakeholders.

Pay

The base salary range for this role is $165,400-$264,700. This range is a good faith estimate, and the amount of base salary will correspond with experience and skill set. This range can also fluctuate depending on demand and location.

This job is eligible for discretionary bonus(es) based on financial performance.

Benefits

Teradyne offers a variety of robust health and well-being benefit programs, including:

• Medical, dental, and vision coverage
• Flexible Spending Accounts
• Retirement savings plans
• Life and disability insurance
• Paid vacation & holidays
• Tuition assistance programs