Engineer II - Digital ASIC Design

About the role

People come to work at Microchip because we help design the technology that runs the world. They stay because our culture supports their growth and stability. They are challenged and driven by an incredible array of products and solutions with unlimited career potential. Microchip’s nationally-recognized Leadership Passage Programs support career growth where we proudly enroll over a thousand people annually. We take pride in our commitment to employee development, values-based decision making, and strong sense of community, driven by our Vision, Mission, and 11 Guiding Values; we affectionately refer to it as the Aggregate System and it’s won us countless awards for diversity and workplace excellence. Our company is built by dedicated team players who love to challenge the status quo; we did not achieve record revenue and over 30 years of quarterly profitability without a great team dedicated to empowering innovation.

Responsibilities

• Follow the micro-architecture and implement RTL (System Verilog) of complex digital IP blocks from concept to delivery.
• Drive Power, Performance, and Area trade-offs and optimizations to meet aggressive product targets.
• Collaborate with SoC integration teams to ensure seamless connectivity and address top-level timing/congestion issues.
• Lead Lint, CDC, RDC, and formal verification efforts.
• Work closely with Physical Design teams to close timing and resolve routing bottlenecks.
• Cooperate with teams to verify and validate module and system functions.
• Organize documents to record design activities.

Requirements

• 2.5 - 5 years of proven experience in ASIC or FPGA digital design.
• BS degree in Electrical Engineering.
• Proficiency in System Verilog and a deep understanding of synchronous/asynchronous design techniques.
• Experience with the full Cadence/Synopsys front-end EDA flow (e.g., VCS, SpyGlass, Design Compiler, PrimeTime).
• Familiarity with PHY or Serdes protocols; knowledge of IEEE 802.3 is a plus.
• Skillful in scripts to aid efficiency.
• Post-silicon validation or bring-up experience; proficient in lab equipment (e.g., oscilloscope, logic analyzer, etc.).

Benefits

• Competitive base pay, restricted stock units, and quarterly bonus payments.
• Health benefits that begin day one.
• Retirement savings plans.
• Industry leading ESPP program with a 2‑year look‑back feature.

Pay

The annual base salary range for this position, which could be performed in the US, is $70,304 - $143,000.* (Range dependent on location, skills, and experience.) Total compensation includes base pay, RSU, and quarterly bonus.

Schedule

Regular business hours; travel time 0%‑25%; work breakdown: 70% sitting, 15% standing, 15% walking.