ASIC/RTL Design Engineer II

About the role

TekWissen is a global workforce management provider offering strategic talent solutions to clients worldwide. This is a 12-month onsite position located in San Jose, CA, with a pay rate of $60.00 - $62.00 per hour.

Responsibilities

• Lead and participate in the design of leading-edge SoCs in advanced digital CMOS processes.
• Contribute to chip definition, architecture development, and modeling.
• Develop micro-architectural specifications and convert them into logic implementation.
• Engage in verification, emulation, debug, synthesis, and timing closure.
• Interface with physical execution, software, and silicon bring-up teams.
• Work with a variety of IPs, including ARM cores, Ethernet, DDR, DMA, PCIe, SATA, and client internal IPs.

Requirements

• Hands-on experience with industry ASIC design flow, including RTL coding, debugging/verification, and supporting synthesis and timing closure.
• Working knowledge of ARM cores and other standard I/O interfaces.

Skills

• Strong communication and documentation skills.
• Good organizational, time management, and multitasking abilities.
• Strong initiative and discipline to follow through on tasks.
• Technical leadership capabilities.