Emulation Engineer

About the role

Arteris enables engineering and design teams at the world’s most transformative brands to connect and integrate today’s system-on-chips (SoCs) that fuel modern innovation. If you’ve held a smartphone, driven an electronic car, or powered up a smart TV, you’ve come in contact with what we do at Arteris. Here, the future is quite literally in your hands—and when it isn’t, chances are it is flying overhead in a drone, a satellite, or in the cloud at a datacenter! As an Emulation Engineer at Arteris, you will work with an expert team to design and deliver interconnect & memory hierarchy solutions for some of the world's most sophisticated mobile, telecom, automotive, and consumer SoC designs. You will create designs in a powerful language that blends traditional RTL with leading-edge software to provide extremely configurable, testable, and high-quality solutions. You will go home at the end of the day amazed at all the places where your creations end up. You will have the opportunity to be part of a proven-successful startup, and to influence development environment, architecture, verification, and everything in-between – you will no longer be stuck in a silo or just a cog in the machine. Your co-workers will be an experienced team of industry experts that love what they do.

Responsibilities

• Maintaining hardware emulation system in full operational condition
• Defining, documenting, developing and executing emulation process for multiple projects
• Integrating hardware emulation system to different software platform
• Triaging regressions, debugging RTL designs in Verilog and SystemVerilog
• Helping improve and refine emulation process, methodology, and metrics

Requirements

• 3+ years’ experience on SoC, system on chip, IPs integration or IP RTL design
• Familiar with Verilog & SystemVerilog programming
• Strong emulation experience working on available platforms such as Palladium, Veloce, or Zebu, as well as experience with compilation, debug, performance, and throughput optimization
• Knowledge of ARM CHI-E/ACE/AXI bus protocol
• Experience of emulator for “SoC + Software” validation
• Siemens Veloce experience is a plus
• Strong skill on signal waveform debugging, such as visualization tools

Qualifications

• MS degree in EE, CS, or equivalent preferred
• BS degree minimum

Skills

• Verilog & SystemVerilog programming
• Emulation platforms (Palladium, Veloce, Zebu)
• Compilation, debug, performance, and throughput optimization
• ARM CHI-E/ACE/AXI bus protocol knowledge
• SoC + Software validation on emulators
• Signal waveform debugging and visualization tools

Pay

Estimated Base Salary: $150,000 - $190,000 Annually