EDA Tools Hardware Engineer

Join Intel's mission to engineer world-changing technology as an EDA Tools Hardware Engineer. This role focuses on developing and maintaining transistor-level timing characterization flows for custom IPs, embedded memories, SRAMs, register files, and compiler-generated macros across advanced semiconductor technologies.

About the role

This position involves characterization methodology, CAD infrastructure, automation, and model validation for complex custom macros and memory IPs. The engineer will collaborate with custom circuit, memory design, STA, and methodology teams to enable scalable and silicon-accurate timing, power, and noise modeling flows.

Responsibilities

• Develop, test, and analyze engineering design automation tools, flows, and methodologies to improve efficiency and optimize power and performance.
• Collaborate with EDA vendors to define, evaluate, and test next-generation design tools and flows.
• Create and verify unique hardware designs, integrating components into hierarchical systems to support end-to-end EDA tool testing for advanced technology nodes.
• Define and enable methodologies for hardware development related to EDA tools and technology node advancements.
• Support and enhance platforms, databases, scripts, and tools used for design automation.
• Provide digital design, verification, full-chip integration, physical layout, power, performance, clocking, and timing for future TFM development.

Requirements

• Bachelor's degree in Computer Engineering, Electrical Engineering, Computer Science, or a related field and 6+ years of relevant experience; OR
• Master's degree in Computer Engineering, Electrical Engineering, Computer Science, or a related field and 4+ years of relevant experience; OR
• PhD in Computer Engineering, Electrical Engineering, Computer Science, or a related field and 2+ years of relevant experience.
• Experience with timing characterization methodologies in one of the following: Nanotime, Liberate, PrimeLib.
• Experience with Liberty timing models.

Skills

• SPICE simulation
• CMOS circuits
• Memory architecture fundamentals
• STA fundamentals
• Advanced-node custom IP or memory characterization flows
• Scripting and automation skills in Linux environments

Benefits

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation.

Pay

Annual Salary Range for jobs which could be performed in the US: $141,910.00 - 269,100.00 USD. The range displayed reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training.

Schedule

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site.

Primary work locations: US, California, Santa Clara. Additional locations: US, California, Folsom; US, Oregon, Hillsboro; US, Texas, Austin.