EDA Tools Hardware Engineer

Join Intel's world-class team as an EDA Tools Hardware Engineer, where you will play a pivotal role in shaping the future of silicon innovation. This position directly contributes to the enablement and adoption of cutting-edge hardware design tools, flows, and methodologies. Your work will enhance the efficiency of design processes and optimize power, performance, and technology node advancements. Collaborate with EDA vendors, define next-generation design tools, and contribute to groundbreaking innovations that enrich lives worldwide.

Responsibilities

• Develop and maintain full-chip physical implementation flows including:
  • Floor planning and partitioning strategies
  • Hierarchical block integration
  • Chip-level placement and routing coordination
  • Power grid planning and analysis
  • Clock tree synthesis (CTS) strategy integration
• Enable scalable SoC assembly flows for multi-block and multi-power domain designs.
• Define methodology for hierarchical design reuse and integration.

Requirements

• Bachelor's degree in Computer Engineering, Electrical Engineering, Computer Science, or a related field with 6+ years of experience; or a Master's degree with 4+ years of experience; or a PhD with 2+ years of experience.
• Physical design fundamentals (e.g., placement, routing).
• Clock tree synthesis (CTS).
• Full-chip integration methodologies using Innovus.

Skills

• Static timing analysis (STA).
• Power grid design and IR drop concepts.
• Experience with large SoC or multi-block design implementation flows.
• Scripting and automation skills in Linux environments.

Benefits

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation.

Pay

Annual Salary Range for jobs which could be performed in the US: $141,910.00 - 269,100.00 USD. The range displayed reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training.

Schedule

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site.

Primary locations: US, California, Santa Clara. Additional locations: US, California, Folsom; US, Oregon, Hillsboro; US, Texas, Austin.