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Director, High Speed SerDes Application Engineering

Marvell Technology · Santa Clara, CA · 4 days ago
EngineeringFull-time

Your Team, Your Impact

Marvell's Central Engineering (CE) organization develops the industry's most advanced High-Speed SerDes (HSS) IPs, covering a broad range of applications including cloud data center, AI/ML infrastructure, 5G wireless, storage, and optical interconnects. Central System Engineering (CSE), a key function within CE, is responsible for validation, characterization, and application engineering support of high-speed SerDes and analog macros for electrical and optical applications. The team also develops data communication system hardware and software infrastructure to deliver the highest quality SerDes IP and analog macros across Marvell's Business Units.

What You Can Expect

As Director of Application Engineering, you will lead a team of application engineers responsible for enabling Marvell's high-speed SerDes IP across internal Business Units and external customers. You will serve as the primary technical authority bridging SerDes IP development and real-world system deployment.

Leadership & Team Management

  • Build, mentor, and manage a high-performing team of application engineers across multiple sites and time zones
  • Define team charter, set technical direction, and drive execution against program milestones
  • Partner with senior managers in CE and Business Units on resource planning, headcount strategy, and budget management

Technical Application Engineering

  • Lead application engineering support for high-speed SerDes IPs (NRZ and PAM4, up to 224G+) across protocols including PCIe, Ethernet (10G–800G), Fibre Channel, CPRI, and CEI
  • Drive bring-up, debug, and characterization of SerDes blocks including PLL/CDR, ADC/DAC, TX FFE, RX CTLE/DFE, and signal integrity optimization
  • Own the development of evaluation kits, reference designs, application notes, white papers, and technical collateral for internal and external use
  • Provide technical leadership on signal integrity analysis, channel modeling, and compliance testing for high-speed electrical and optical interfaces

Customer & Business Unit Engagement

  • Act as the senior technical interface between CE SerDes IP and Marvell Business Units (Networking, Storage, Compute, Custom ASIC)
  • Engage directly with key customers and partners on design reviews, system bring-up, and performance optimization
  • Identify new application opportunities and provide product definition input to Design and Marketing teams
  • Represent Marvell at industry conferences, standards bodies (IEEE, OIF, PCI-SIG), and customer technical forums

Cross-Functional Collaboration

  • Collaborate with SerDes design, DSP algorithm, and physical design teams to ensure IP is production-ready and customer-deployable
  • Work with the SW team to define and deliver APIs and firmware enabling BU integration of CE SerDes in SoC products
  • Drive alignment on test methodology, compliance frameworks, and customer support processes across the organization

What We're Looking For

  • 5+ years in direct people management and technical leadership
  • Deep expertise in high-speed SerDes architecture, analog/mixed-signal circuits, and data communication systems (NRZ and PAM4 at 56G, 112G, 224G+)
  • Strong hands-on background in post-silicon bring-up, lab characterization, and signal integrity — including proficiency with oscilloscopes, BERTs, VNAs, and spectrum analyzers
  • Solid understanding of high-speed interface protocols and standards: PCIe Gen5/6, 100G/400G/800G Ethernet, Fibre Channel, CPRI, OIF CEI
  • Experience with high-speed PCB design, channel simulation (ADS, HSPICE), and compliance testing
  • Proven ability to lead multi-disciplinary teams and drive results across complex, matrixed organizations
  • Excellent communication and presentation skills; comfortable engaging with executives, customers, and standards bodies
  • Ability to travel domestically and internationally as needed (~20%)

Preferred Qualifications

  • Experience with electro-optical systems and optical transceiver applications
  • Familiarity with scripting and automation (Python, MATLAB, C/C++) for test and characterization workflows
  • Background in AI/ML infrastructure or hyperscale data center applications
  • Prior experience working with or within a semiconductor IP organization

Pay

Expected base pay range: $190,280 - $285,000 per annum. The successful candidate's starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions.

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