Digital Verification Engineer

Responsibilities

• Collaborate with architecture, systems, and design teams to understand product requirements and develop verification plans to meet project specifications.
• Perform functional simulations and design debugs.
• Develop functional (digital) verification plans, test cases, Verification IP, and test bench components.
• Understand development boards and lab equipment to perform digital silicon validation.
• Develop infrastructure and test cases targeted for IP, sub-system, or SoC level.
• Create and execute test plans for design functionality.
• Design, implement, and improve UVM test benches.
• Run coverage and regression, analyze coverage gaps, and devise strategies to achieve higher code coverage.
• Debug silicon, develop scripts, and automate coverage reports.
• Refine test cases and simulation models.
• Collaborate with different functional groups to support successful product release.

Requirements

• Master’s degree in Electrical Engineering, Electronics Engineering, Computer Engineering, or a related field.

Skills

Position requires knowledge gained via completion of a graduate-level course, internship, or related occupation involving:

• Computer Architecture
• Digital Integrated Circuit Design
• Microprocessor system design
• Verilog and System Verilog
• Formal verification
• Programming languages: Python or C/C++, SQL
• Jenkins
• Data warehouse using Informatica
• Troubleshooting and debugging

Pay

$124,800 per year