Digital Verification Engineer

Job Description & Responsibilities

We are looking for ASIC Design Verification Engineers with strong CPU, ASIC design and verification fundamentals to work in Neuralink’s System-on-Chip (SoC) department under the Implant Team. This position offers a rare and unique opportunity to have a high impact in realizing state-of-the-art brain-computer interfaces. The team delivers architecture and logic implementation of digital modules with a strong focus in high-throughput low-power digital signal processing (DSP).

• Deliver architecture and logic implementation of digital modules.
• Focus on high-throughput low-power digital signal processing (DSP).
• Work on complex digital systems from architecture, microarchitecture, RTL, verification and physical design using industry standard tools.
• Develop test benches, testing, and debugging for a complex system-on-chip.
• Build formal verification and low power formal verification flows.
• Implement and utilize UVM for verification methodologies.
• Work with ARM/RISC-V processor, AMBA bus, and knowledge of power aware verification.
• Experience with FPGA/emulation and lab system bring up, writing diagnostic, and lab debugging.

Key qualifications

• Minimum 3 years of experience in digital ASIC verification.
• Excellence in SystemVerilog.
• Experience in developing automation flow and scripts such as Python, Perl, Makefile, Tcl and UNIX shell.
• Experience with code coverage and regression setup.

Preferred qualifications

• Experience working on complex digital systems from architecture, microarchitecture, RTL, verification and physical design using industry standard tools.
• Experience on building test benches, testing, and debugging for a complex system-on-chip.
• Experience in formal verification.
• Functional modeling experience and logic verification with SystemVerilog, SystemC/C++.
• Experience with IEEE-1801 (UPF) based design simulation flows.
• Experience with low power gate level simulations.
• Exposure with low power formal verification flows.
• Strong hands-on experience in verification methodologies such as UVM.
• Knowledge of ARM/RISC-V processor, AMBA bus.
• Experience with FPGA/emulation.
• Experience with lab system bring up, writing diagnostic, and lab debugging.

Expected Compensation

The anticipated base salary for this position is expected to be within the following range. Your actual base pay will be determined by your job-related skills, experience, and relevant education or training. We also believe in aligning our employees’ success with the company's long-term growth. As such, in addition to base salary, Neuralink offers equity compensation (in the form of Restricted Stock Units (RSU)) for all full-time employees.

Base Salary Range: $131,000 USD - $243,000 USD

What We Offer

• Full-time employees are eligible for the following benefits listed below.
• An opportunity to change the world and work with some of the smartest and most talented experts from different fields.
• Growth potential; we rapidly advance team members who have an outsized impact.
• Excellent medical, dental, and vision insurance through a PPO plan.
• Paid holidays.
• Commuter benefits.
• Meals provided.
• Equity (RSUs).
• 401(k) plan.
• Parental leave.
• Flexible time off.