Digital Design RTL Engineer

Responsibilities

• Operate with a high degree of autonomy, taking designs from initial specification through to timing closure and physical design hand-off
• Collaborate cross-functionally with Architecture, Verification, and Physical Design teams to mitigate risks and ensure project milestones are met on schedule
• Show high proficiency in SystemVerilog
• Show proven track record of delivering high-quality SystemVerilog RTL in advanced process nodes (5nm and below) and possesses a deep understanding of PPA optimization, clock domain crossing (CDC) analysis, and low-power design techniques
• Show experience with SoC integration, high-speed SerDes, LPDDR/DDR, and/or HBM protocols

Requirements

• BSEE required, MSEE/PHD preferred
• 8+ years of industry experience with a focus on SoC integration, high-speed SerDes, LPDDR/DDR, and/or HBM protocols is highly preferred

Qualifications

Proven track record of delivering high-quality SystemVerilog RTL in advanced process nodes (5nm and below)

Skills

• Deep understanding of RTL Design
• PPA optimization
• Clock Domain Crossing (CDC) analysis
• Low-power design techniques

Benefits

• Medical
• Dental and vision plans
• 401(K) participation including company matching
• Employee Stock Purchase Program (ESPP)
• Employee Assistance Program (EAP)
• Company paid holidays
• Paid sick leave and vacation time

Pay

The annual base salary range for this position is To

Schedule

N/A

Benefits

• Competitive and comprehensive benefits package
• Applicable laws for Paid Family Leave and other leaves of absence