DFT Technical Leader

Application window expected to close on 10/01/2026; posting may be removed earlier if the position is filled or sufficient applications are received.

About the Team

The Common Hardware Group (CHG) creates innovative hardware platforms central to the AI era, powering Cisco’s core Switching, Routing, and Wireless products for organizations globally. Our innovations in silicon, optics, and hardware platforms—like Silicon One—are shaping the technology industry. We're a global team of creative experts, bringing unique backgrounds and bold ideas to push boundaries and help each other grow. Because full product development—from design to qualification to production—is within our team, we’re able to think differently, experiment more, and work quickly.

Responsibilities

• Implement Hardware Design-for-Test (DFT) features that support ATE, in-system test, debug, and diagnostics needs of the designs.
• Develop innovative DFT IP in collaboration with multi-functional teams and play a key role in full-chip design integration with testability features coordinated in the RTL.
• Work closely with design, design-verification, and physical design teams to enable integration and validation of test logic in all phases of implementation and post-silicon validation flows.
• Participate in creating innovative hardware DFT and physical design aspects for new silicon device models, bare die, and stacked die, driving reusable test and debug strategies.
• Craft solutions and debug with minimal mentorship.

Requirements

• Bachelor's or Master's Degree in Electrical or Computer Engineering with at least 10 years of experience.
• Experience with the latest trends in DFT, test, and silicon engineering.
• Experience with JTAG protocols, scan and BIST architectures, including memory BIST and boundary scan.
• Experience with ATPG and EDA tools like TestMax, Tetramax, Tessent toolsets, and PrimeTime.
• Experience with gate-level simulation and debugging using VCS and other simulators.
• Post-silicon validation and debug experience; ability to work with ATE patterns and P1687.

Preferred Qualifications

• Verilog design experience, including developing custom DFT logic and IP integration, and familiarity with functional verification.
• DFT CAD development: test architecture, methodology, and infrastructure.
• Test static timing analysis.
• Post-silicon validation using DFT patterns.
• Verification skills including SystemVerilog, logic equivalency checking, and validating test-timing of the design.

About Cisco

At Cisco, we’re revolutionizing how data and infrastructure connect and protect organizations in the AI era—and beyond. We’ve been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across their entire digital footprint. Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere. We are Cisco, and our power starts with you.

Pay

The starting salary range for this position is $183,800.00 to $263,600.00 for new hires in U.S. and/or Canada locations, not including incentive compensation, equity, or benefits. Individual pay is determined by the candidate's hiring location, market conditions, job-related skillset, experience, qualifications, education, certifications, and/or training.

Full salary ranges for specific locations:

• New York City Metro Area: $183,800.00 - $303,100.00
• Non-Metro New York State & Washington State: $163,600.00 - $269,800.00

For quota-based sales roles, the ranges include base pay and sales target incentive compensation combined.

Benefits

• Medical, dental, and vision insurance.
• 401(k) plan with Cisco matching contribution.
• Paid parental leave, short and long-term disability coverage, and basic life insurance.
• Paid time off:
  • 10 paid holidays per full calendar year, plus 1 floating holiday for non-exempt employees.
  • 1 paid day off for employee’s birthday, paid year-end holiday shutdown, and 4 paid days off for personal wellness.
  • Non-exempt employees receive 16 days of paid vacation time per full calendar year, accrued at 4.92 hours per pay period.
  • Exempt employees participate in Cisco’s flexible vacation time off program with no defined limit (subject to business limitations).
  • 80 hours of sick time off provided on hire date and each January 1st thereafter, with up to 80 hours of unused sick time carried forward.
  • Additional paid time away for critical or emergency family issues.
  • Optional 10 paid days per full calendar year to volunteer.
• Annual bonuses for non-sales roles, subject to Cisco’s policies.
• For sales roles, performance-based incentive pay split between quota and non-quota components:
  • Quota-based incentive pay:
    • 0.75% of incentive target for each 1% of revenue attainment up to 50% of quota.
    • 1.5% of incentive target for each 1% of attainment between 50% and 75%.
    • 1% of incentive target for each 1% of attainment between 75% and 100%.
    • Once performance exceeds 100% attainment, incentive rates are at or above 1% for each 1% of attainment with no cap.
  • Non-quota-based sales performance elements: 0% up to 125% of target.
• Eligibility for grants of Cisco restricted stock units, vesting after continued employment.