Jobs · Information Technology · California

DFT Implementation Lead

Eliyan Corporation · San Francisco, CA · 1 mo ago
On-siteInformation TechnologyFull-time

About the role

Join the leading chiplet startup! As an Eliyan DFT Implementation lead, you will be working at a fast-paced early-stage startup creating technologies that fuel tomorrow’s chiplet based systems with best-in-class power, area, manufacturability, and design flexibility. You will be responsible for crafting DFT implementation schemes for best-in-class PHYs and Controllers. You will work with a cross-functional team of experts that operate from first principles, innovate and push the envelope to create high-volume and high-performance manufacturable products.

Responsibilities

  • Develop and implement innovative DFT IP and features to support ATE, in-system test, debug, and diagnostics.
  • Contribute to flow and methodology development working closely with the digital, analog and physical design teams.
  • Collaborate with cross-functional teams to integrate DFT features into the RTL design and ensure seamless validation and verification.
  • Work closely with the STA methodology owner in defining hierarchical DFT constraints and multi-mode multi-corner sign-off.
  • Produce area/power tradeoff against design choices made for improved DFT coverage.
  • Own complete architecture, tool/vendor selection for DFT insertion, simulation, fault debug and characterization.
  • Work closely with design, design-verification, and physical design teams to enable the integration and validation of test logic.
  • Participate in the development of innovative hardware DFT and physical design aspects for new silicon device models.
  • Create and maintain dashboards for tracking DFT collaterals to be handed over to Test Engineering, including coverage matrix.
  • Responsible to produce a DFT architecture document for every PHY / chiplet programs specifying a detailed list of collaterals for customers.
  • Work closely with physical implementation teams to define the optimal MMMC corners for various stages of implementation vis-à-vis placement, CTS and routing for DFT modes.
  • Own the DFT architecture for 2.5D/3DIC multi

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