DFT Application Engineer

About the role

Intel Foundry Services is a systems foundry focused on delivering cutting-edge silicon process and packaging technology for the AI era. Our mission includes supporting Aerospace, Defense, and Government (ADG) customers through comprehensive DFT solutions and customer engagement.

Responsibilities

• Provide technical support to Intel Foundry Services customers on PDKs, DFT/DFM insertion, and ATPG validation methodologies.
• Work closely with internal Intel teams and external stakeholders including foundry customers' design teams, IP providers, and EDA vendors to resolve complex technical issues.
• Deliver customer-facing technical support and guidance on DFT implementation strategies.
• Drive quality improvements in ASIC DFT/DFM and ATPG validation methodology, capability/flow, and documentation for both block-level and SoC-level implementations.
• Collaborate with RTL and Hard IP designers on DFT/DFM implementation methodology and work with physical designers on DFT/DFM physical implementation, validation, and timing signoff.
• Develop and optimize DFT insertion flows for advanced CMOS processes and multi-die designs.
• Technical Content Development & Training: Develop application notes, comprehensive documentation, and deliver technical training presentations to customers and internal teams. Create best practice guidelines and methodology documentation for DFT implementation across various design complexities. Support knowledge transfer and capability building for both internal teams and customer organizations.

Qualifications

• US Citizenship required.
• Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, or STEM-related field; 3+ years of experience with advanced CMOS processes (22nm and below); 3+ years of combined experience in implementing ASIC DFT/DFM insertion (MBIST, LBIST, SCAN, JTAG) at both ASIC design block level and full chip level, including ATPG validation and DFT timing/signoff at SOC level; 2+ years of experience in scripting languages (Python, Perl, Tcl, and/or shell scripting).
• Preferred qualifications: Active US Government Security Clearance with a minimum of Secret Level; Post-graduate degree in Electrical/Computer Engineering or STEM-related field; Hands-on experience in Design Implementation and methodology (ASIC design, Fullchip Integration, Design Signoff, LVS, DRC, DFX/DFM, Reliability); Proficiency with major EDA tools for MBIST insertion, hierarchical SCAN and JTAG insertion, DFT constraint generation and ATPG validation for single die and multi-die designs; Experience building/developing quality DFT/DFX insertion flow and ATPG validation flow; Experience providing technical direction to engineering teams and customer support; Customer-facing experience in technical roles; Experience with state-of-the-art process technology (7nm and below) and PDK-based technology evaluation.

Benefits

• Competitive compensation
• Stock bonuses
• Benefit programs including health, retirement, and vacation