Design Verification Engineer - Quantum Computing (Onsite, Milpitas, CA)

About the role

This is a 3‑month contract (conversion to FTE likely), 40 hour/week onsite position at the client’s offices in Milpitas, CA. The role is a W‑2 position employed by Stage 4 Solutions.

Responsibilities

• Verification planning and requirements traceability
• Testbench architecture and development
• Reusable verification IP
• UVM components including BFMs, drivers, monitors, checkers, reference models, and scoreboards
• SystemVerilog Assertions (SVA)
• Constrained‑random and directed testing
• Functional and code coverage analysis and closure
• Regression setup, CI, and automation
• Debugging RTL/design and testbench issues
• Verification results analysis
• End‑to‑end ownership of verification, including reviewing requirements and design specifications; developing and maintaining verification plans, test specifications, and testbench documentation; identifying corner cases; defining verification and sign‑off criteria; establishing coverage goals and metrics; developing positive, negative, error‑injection, stress, and boundary‑condition tests; executing regressions; triaging failures; driving defects through closure; achieving coverage closure; and providing clear verification status, coverage reports, regression results, and sign‑off documentation
• Work closely with FPGA/RTL, firmware, architecture, and validation teams, maintain a high standard of quality and technical rigor, proactively identify verification risks, gaps, and dependencies, and deliver verification milestones against committed schedules
• Communicate verification status, risks, blockers, and schedule impacts clearly to the broader engineering team

Requirements

• 5+ years hardware design verification and test experience
• Strong hands‑on experience with SystemVerilog/UVM and Xcelium
• Experience with Python/scripting, Git, Linux‑based development environments, simulation/debug tools, CI infrastructure, and regression automation is highly desirable
• Experience verifying FPGA‑based systems, high‑speed interfaces and protocols such as multi‑gigabit serial transceivers (GTY/GTH) (MUST), Ethernet, Aurora/GT link, LVDS, and high‑speed streaming data paths, as well as control/status interfaces, synchronization/timing logic, clock/reset behavior, protocol compliance, or hardware/firmware interactions
• Strong debugging, problem‑solving, documentation, communication, and collaboration skills
• Ability to work independently, take ownership, and drive verification activities from requirements through final sign‑off
• BS/MS in Electrical Engineering, Computer Engineering, or a related field

Benefits

• Health benefits
• 401K

Pay

$90/hr – $100/hr

Schedule

40 hour/week