Design Verification Engineer II – CPU Subsystem

About SiFive

As the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive applications in the world. SiFive’s unrivaled compute platforms are enabling leading technology companies around the world to innovate, optimize, and deliver the most advanced solutions of tomorrow across every market segment of chip design, including artificial intelligence, machine learning, automotive, data center, mobile, and consumer. With SiFive, the future of RISC-V has no limits.

Job Description

The Role: SiFive is looking for a Design Verification Engineer II to drive verification of CPU subsystem functionality in high-performance core development. This is an Engineer II individual-contributor role for an engineer who can independently own complex verification problems, define strategy for their subsystem, and raise methodology quality across the broader CPU DV effort. The role is suited for engineers working on one or more CPU subsystem areas such as Frontend, Midcore, Load-Store Unit, memory ordering and consistency, hardware prefetch, or related microarchitectural interactions. You will work closely with architecture, RTL, performance, compiler, system verification, and software teams to ensure design intent is captured correctly, risks are identified early, and signoff quality is achieved.

Responsibilities

• Own verification planning and execution for one or more CPU subsystem areas, from block-level verification through subsystem integration and signoff.
• Review specifications and microarchitecture from a verification perspective, identify ambiguity early, and influence design quality and debuggability.
• Develop and maintain scalable verification environments, checkers, scoreboards, assertions, stimulus, and coverage models for complex CPU subsystem behavior.
• Define and execute directed and constrained-random test scenarios that expose corner cases in pipeline interactions, load/store ordering, hazard handling, memory consistency, and related subsystem behavior.
• Drive failure analysis and root-cause debug across specification, RTL, test content, and verification infrastructure.
• Write functional coverage, analyze code and functional coverage, and close coverage holes to ensure verification completeness and signoff quality.
• Contribute reusable verification methodology, automation, and infrastructure improvements that increase quality and productivity across future CPU generations.
• Partner effectively across design, architecture, compiler, performance, and system teams to close verification gaps from multiple perspectives.

Minimum Qualifications

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field
• Strong hands-on experience with SystemVerilog and UVM-based verification
• Direct experience with CPU/core verification and solid understanding of computer architecture and CPU microarchitecture
• Experience in one or more CPU subsystem areas such as Frontend, Midcore, Load-Store Unit, memory ordering and consistency, or hardware prefetch verification
• Strong knowledge of verification flow methodology, including test planning, stimulus generation, failure analysis, coverage analysis, and closure
• Strong debug skills and the ability to translate architectural intent into effective verification strategy and execution

Preferred Qualifications

• Experience with out-of-order core verification
• Experience using formal verification, emulation, or performance-oriented verification for high-risk or performance-sensitive problems
• Experience mentoring engineers and influencing verification methodology beyond the immediate block or feature area
• Familiarity with Python, C/C++, or other scripting/programming languages used for DV infrastructure and automation
• Strong interpersonal skills and the ability to influence people across disciplines