Design Verification Engineer

Responsibilities

• Strong understanding of SV and UVM and good debugging skills
• Understanding of AMBA protocols
• Understand design specs and develop test plans based on functional and architectural requirements
• Build UVM/System Verilog-based verification environments for IP/subsystem/SoC level testing
• Develop directed and random testcases, perform coverage analysis, and close functional/code coverage
• Debug simulation failures and work closely with RTL designers to resolve issues
• Execute regression runs, analyze results, and contribute to continuous improvements
• Integrate and run power-aware simulations, low power checks, and work with UPF/CPF as needed
• Collaborate with DFT/PD/RTL teams and post-silicon validation to ensure design quality across domains
• Document test environments, testplans, and results for internal and external reviews

Requirements

• 3-5 years of experience in VLSI HVL Verification

Skills

• SV (System Verilog)
• UVM (Universal Verification Methodology)
• AMBA protocols
• Debugging
• RTL design collaboration
• Power-aware simulations and low power checks (UPF/CPF)

Pay

The expected compensation for this role ranges from $45,000 to $121,000. Final compensation will depend on various factors, including geographical location, minimum wage obligations, skills, and relevant experience.

Benefits

• Full range of medical and dental benefits options
• Disability insurance
• Paid time off (inclusive of sick leave)
• Other paid and unpaid leave options