Design Verification Engineer
About the role
Intel is seeking a Design Verification Engineer for the Silicon Chassis team. In this role, you will contribute to verification of next-generation interconnect and chassis IPs that scale across multiple product families. You will work closely with senior engineers to build and execute robust verification plans, develop high-quality reusable environments, and help deliver first-pass silicon success through strong design verification practices. This role requires strong programming and algorithmic problem-solving skills, hands-on verification development, and willingness to work across traditional discipline boundaries. AI-assisted workflows are part of everyday development here.
Responsibilities
- Develop and execute verification plans and testbenches for interconnect and chassis IP/features at IP and subsystem level
- Build reusable verification components, checkers, constrained-random tests, and debug infrastructure to improve coverage and productivity
- Work with architecture, design, and software teams on spec reviews, feature clarification, bug triage, and closure; contribute outside strict DV boundaries when needed
- Analyze simulation failures, root-cause issues quickly, and drive fixes to closure with clear technical communication
- Contribute to functional coverage planning, coverage closure, and quality signoff under guidance of technical leads
- Contribute to both simulation and formal verification efforts; continuously improve verification automation, regression quality, and development efficiency
- Demonstrate proven ability to write clean, reusable, and maintainable verification code and automation scripts, and to collaborate effectively across architecture, design, and software teams
Qualifications
Minimum Qualifications
- Bachelor's degree in Electrical Engineering, Computer Science, or a related field with 5+ years of industry experience OR Master's degree with 4+ years of relevant experience (post-graduation)
- Programming fundamentals and algorithmic problem-solving skills, with demonstrated hands-on coding experience in SystemVerilog, C/C++, and Python
- Foundation in simulation-based verification methodologies UVM/ABV, with exposure to formal verification concepts; testbench development, debugging, and coverage-driven verification
- Hands-on experience using AI-assisted development tools as part of daily workflow for coding, debugging, and test development
- Exposure to interconnects and bus protocols such as AMBA AXI/ACE/CHI, PCIe, CXL, UCIe
Preferred Qualifications
- Understanding of cache coherency and memory consistency models
- Experience with external interfaces and system integration debug
- Experience with formal verification tools (JasperGold, VC Formal, or similar) and emulation or FPGA-based verification
- Exposure to RTL concepts, physical design, or CAD tool flows
- Prior work with system IPs such as MMUs, SMMU or IOMMU, and interrupt controllers
Skills
- SystemVerilog, C/C++, Python
- UVM/ABV verification methodologies
- Coverage-driven verification
- Formal verification concepts
- AI-assisted development tools
- Interconnect/bus protocols: AMBA AXI/ACE/CHI, PCIe, CXL, UCIe
Benefits
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation.
Pay
Annual Salary Range for jobs which could be performed in the US: $141,910.00 - $200,340.00 USD. The range reflects the minimum and maximum target compensation for the position across all US locations. Individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training.
Schedule & Work Model
Shift 1 (United States of America). This role is eligible for a hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site.
Location
Primary: US, California, Santa Clara. Additional: US, Texas, Austin.