Design Verification Engineer

About the role

Broadcom's ASIC Products Division (APD) is seeking an experienced verification engineer to lead modeling and verification activities for complex digital and mixed-signal (MXS) IP blocks used in Broadcom’s ASIC developments. The role involves defining verification plans and environment architecture, developing test cases and test bench components, coverage analysis and closure, and debug. You may also work with emulation and FPGA prototyping platforms and drive the adoption of advanced verification methodologies and flows.

The engineer will develop functional models to facilitate block, system, and ASIC-level verification, collaborating closely with design teams and EDA vendors.

Responsibilities

• Define verification plans and environment architecture for complex digital and mixed-signal IP blocks.
• Develop test cases, test bench components, and functional models using SystemVerilog and UVM.
• Implement and achieve coverage goals through random and directed test cases, and SystemVerilog Assertions.
• Analyze and debug simulation failures at the RTL and gate-level.
• Work with RTL, gate-level netlists, and SDF, analyzing these formats in a verification context.
• Collaborate with design teams and EDA vendors to accomplish modeling and verification tasks.
• Evaluate and drive adoption of advanced verification methodologies and flows, potentially involving emulation (Palladium, Veloce, Zebu) and FPGA (Xilinx) platforms.
• Develop automated processes to improve verification efficiency.
• Work independently and within a global team in a highly visible, dynamic environment.

Requirements

• 12+ years of experience with verification concepts and architectures for complex digital and mixed-signal circuits.
• Experience verifying designs at the block and system levels.
• Experience with complex digital and mixed-signal circuits (PLL, DLL, ADC, DAC).
• Proficiency in debugging RTL and gate-level netlists, and analyzing schematic diagrams of analog/mixed-signal circuits.
• Expertise in SystemVerilog and advanced verification methodologies (UVM, SVA).
• Experience with Synopsys, Cadence, and Mentor simulation tools.
• Ability to plan and deploy complex, reusable, and scalable verification environments.
• Proficiency in scripting languages (Perl/Python, Tcl).
• Experience with version control systems (DesignSync, git).
• Strong writing, grammar, and verbal communication skills.
• Excellent problem-solving skills with a focus on automation.
• Ability to learn and adapt to new tools and methodologies quickly.
• Legal authorization to work in the U.S.

Qualifications

• BS in Electrical Engineering or Computer Engineering with 12+ years of related experience; or an MS in Electrical Engineering or Computer Engineering with 10+ years of related experience.

Preferred Skills

• Hardware design and debug experience.
• Experience with emulation platforms (Palladium, Veloce, Zebu) and FPGA (Xilinx).
• Formal verification concepts or experience.
• Experience verifying iJTAG networks using ICL and PDL in the Tessent tool.
• Co-simulation experience.

Pay

The annual base salary range for this position is USD 143,800 to USD 230,000.

Benefits

• Discretionary annual bonus.
• Competitive new hire equity grant and annual equity awards.
• Comprehensive medical, dental, and vision plans.
• 401(K) participation with company matching.
• Employee Stock Purchase Program (ESPP).
• Employee Assistance Program (EAP).
• Paid holidays, sick leave, and vacation time.
• Paid Family Leave and other leaves of absence in compliance with applicable laws.