Design Verification Engineer

About the Role

We are seeking a highly experienced and visionary Lead/Principal ASIC Design Verification Engineer to drive the verification strategy for our next-generation silicon. In this role, you will oversee and execute both block-level and system-level verification, ensuring the architectural integrity of complex SoC designs. You will collaborate closely with cross-functional design and verification teams to resolve complex trade-offs and deliver high-quality silicon on advanced node technologies.

Responsibilities

• Lead and execute comprehensive verification strategies at both the block and system levels.
• Define, deploy, and enhance advanced ASIC design verification flows and DV methodologies.
• Build robust, scalable, object-oriented verification environments and testbenches.
• Independently debug complex design and verification issues; analyze and resolve intricate verification trade-off scenarios.
• Partner closely with design and verification teams to ensure alignment on coverage, timelines, and architectural goals.

Qualifications

• Bachelor’s Degree in Electrical and Electronic Engineering, Computer Science, or a related field.
• 17+ years of relevant industry experience in ASIC design verification (preferred).
• Deep fluency in RTL verification methodologies, including SystemVerilog.
• Strong working knowledge of object-oriented verification languages UVM, C/C++, and scripting languages (Perl, Python, or Tcl).
• Experience working with advanced process node technologies (e.g., 5nm and below) is highly desired.
• Exceptional verbal and written communication skills; proven ability to thrive and lead in a collaborative team environment.
• Must have legal authorization to work in the US.

Preferred Skills

• Experience with hardware design, hardware debugging, and SystemC or other programming languages.
• Hands-on experience with hardware emulation (e.g., Palladium, Zebu) and FPGA-based prototyping.
• Broad familiarity with overall chip design methodologies, EDA tools, and front-to-back silicon development lifecycles.

Pay

The annual base salary range for this position is USD 150,800.00 to USD 241,200.00.

Benefits

• Discretionary annual bonus
• Competitive new hire equity grant and annual equity awards
• Medical, dental, and vision plans
• 401(K) participation including company matching
• Employee Stock Purchase Program (ESPP)
• Employee Assistance Program (EAP)
• Company paid holidays, paid sick leave, and vacation time
• Paid Family Leave and other leaves of absence as required by law