Design Engineering Intern

Responsibilities

• Perform design database management;
• Proper check-in’s of golden files, reverting unused changes, merge different files.
• Code RTL logic with Verilog syntax.
• Run simulation using Synopsys VCS.
• Debug simulation environment; compilation failure, simulation hang, simulation functional failure, etc.
• Communicate with designers, verification engineers, and other team for the correct solution.

Requirements

• BS/MS degree (completed or in progress) in Electrical Engineering, Electronics, Computer Science, or a related field.
• Proficiency in Verilog, SystemVerilog programming language.
• Good communication within co-working environments.
• Good work ethic, i.e. punctual on deadline, trustworthy commitment on assignment.
• Available to work 40 hours per week, Monday – Friday.
• 100% onsite commitment for a 6-month duration.

Qualifications

• Have a mindset on problem solving.
• Understand ASIC/FPGA workflow from concept to real silicon.
• Scripting language skills such as Python, Perl, Tcl, etc. (preferred).

Compensation

$35/hr - $45/hr