Design Engineer – AI SoC Development

About the role

Join Intel's AI Revolution. Intel's AI SoC organization develops cutting-edge products powering a wide range of AI applications, from edge devices to data center accelerators. This role involves developing logic design, register transfer level (RTL) coding, and simulation for SoC designs, integrating IP blocks and subsystems into full chip SoC or discrete component designs.

Responsibilities

• Contribute to evaluation of architectural trade-offs considering features, performance, and system constraints
• Implement RTL in Verilog/System Verilog based on defined micro-architecture
• Integrate IP blocks at top level and ensure synthesis- and timing-clean design
• Work closely with verification teams to achieve full coverage and robust validation
• Develop timing constraints for IP blocks and assist physical design teams with synthesis, timing closure, and formal equivalence checks
• Support silicon bring-up and post-silicon validation activities, including debug and performance analysis
• Collaborate with senior engineers to adopt best practices and improve design methodologies
• Drive quality assurance compliance for smooth IP/SoC handoff
• Work with IP providers to integrate and validate IPs at the SoC level

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, or Computer Science
• 4+ years of experience in/with: RTL design and implementation for ASIC/SoC development
• Proficiency in Verilog/System Verilog for RTL coding and design
• Experience with synthesis tools and timing closure methodologies

Preferred Qualifications

• Understanding of clock domain crossings, power optimization, and timing closure
• Exposure to SoC system integration and CPU subsystem design
• Familiarity with standard bus protocols (AXI, AHB, etc.) and embedded processor architectures
• Knowledge of high-speed and low-power design techniques
• Experience with static timing analysis (STA) tools and methodologies
• Hands-on experience with formal verification tools and techniques
• Basic scripting skills (Python, TCL, etc.) for automation
• Experience with EDA tools: HDL simulators (VCS, Questa, IES), lint tools (Spyglass), and FPGA prototyping tools

Pay

$164,470.00 - 232,190.00 USD

Schedule

Shift 1 (United States of America)