DDR PHY Signal Integrity and Power Integrity Engineer

About the role

We are looking for an experienced signal integrity and power integrity engineer to join the CT Server DDR team. In this role, you will be responsible for DDR PHY channel and power delivery network (PDN) architecture, system-level SI/PI, and post-silicon validation.

Responsibilities

• Run system-level channel and PDN simulations (insertion/return loss, crosstalk, eye diagrams, impedance, IR drop, jitter transfer) and correlate with silicon results
• Process post-silicon SI/PI validation data and drive the next steps
• Debug SI/PI issues across silicon, package, and board, working with firmware and design teams
• Support cross-functional teams with system, channel, PDN, and decoupling implementation details
• Define channel and PDN architectures, model signal and power delivery at the system level, and validate SI/PI on silicon
• Work with design, package, board, and firmware teams on the specification of SI/PI targets and their implementation
• Help debug issues across the full system stack

Qualifications

• Bachelor’s or Master’s degree in Computer Engineering or Electrical Engineering
• Strong coding skills in Python and Matlab preferred
• Signal integrity (SI) and power integrity (PI) knowledge, including S-parameter/Z-parameter analysis, channel modeling, and PDN modeling
• Knowledge of Ansys or Cadence simulation tools (e.g., HFSS, SIwave, Sigrity, Clarity)
• System-level experience with firmware and hardware debug expertise preferred
• System modeling with silicon-to-simulation correlation
• Firmware development for ATE and platforms

Location

Santa Clara, CA (open to other locations)

Work Site Type: Onsite/Hybrid