Custom SOC IP Verification Engineer

NVIDIA is seeking a Senior Custom SOC/IP Verification Engineer to verify the next generation SoC and IP solutions. We are looking for motivated individuals with a desire to deliver innovative products and build the next generation of life-changing custom SOCs.

About the role

This role requires a skilled ASIC Verification Engineer with expertise in fabric and interconnect verification, spanning both IP and SoC integration. You will play a key role in verifying the correctness, performance, and compliance of on-chip fabrics and interconnect subsystems — from IP bring-up through full chip integration — ensuring robust and high-performance connectivity across complex SoC designs.

Responsibilities

• Responsible for ASIC design verification of fabric and interconnect IP blocks as well as full chip integration, covering DMA, routing, arbitration, ordering, flow control, and protocol compliance.
• Develop and implement test plans for fabric and interconnect verification of SoCs using UVM-based environments, targeting both IP-level and system-level scenarios.
• Design and implement constrained-random and directed SystemVerilog testbenches targeting interconnect fabrics, network-on-chip (NoC) topologies, and multi-agent SoC integrations.
• Collaborate extensively with Architecture, SW/FW, Design, Modeling, Emulation, and Post-Silicon Validation teams to ensure comprehensive first-time right verification plans and execution.
• Drive the development of silicon and platform verification strategies and methodologies for fabric and interconnect subsystems.

Requirements

• B.S. or M.S. degree in Computer Engineering, Electrical Engineering, or a related field (or equivalent experience).
• 5+ years of experience in ASIC verification, with a strong focus on fabric, interconnect, or network-on-chip verification at both IP and full chip levels.
• Strong knowledge of SystemVerilog and UVM methodology.
• Hands-on experience with industry-standard interconnect and bus protocols (e.g., AMBA AXI, CHI, or equivalent), with solid understanding of ordering, coherency, and flow control semantics.
• Familiarity with SoC architectures, NoC topologies, and multi-initiator/multi-target interconnect designs.
• Proficiency in scripting languages (Python, Perl, TCL).

Skills

• Knowledge of performance verification and bandwidth/latency analysis for interconnect fabrics.
• Exposure to verification IPs for bus protocols, or emulation platforms (e.g., Palladium, Veloce) for full chip fabric validation.
• Experience in GPU or AI accelerator SoC interconnect verification is desirable.
• Experience with formal verification or assertion-based verification (SVA) applied to fabric and protocol properties.

Pay

Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 136,000 USD - 218,500 USD for Level 3, and 168,000 USD - 264,500 USD for Level 4. You will also be eligible for equity and benefits.

Benefits

NVIDIA offers highly competitive salaries and a comprehensive benefits package. For more details, visit www.nvidiabenefits.com.