Custom SOC IP Verification Engineer

NVIDIA has been transforming computer graphics, PC gaming, and accelerated computing for more than 25 years. Today we are tapping into the unlimited potential of AI to define the next era of computing, where our GPUs act as the brains of computers, robots, and self‑driving cars. As a Senior Custom SOC/IP Verification Engineer you will verify next‑generation SoC and IP solutions, ensuring robust and high‑performance connectivity across complex designs.

About the role

This position requires a skilled ASIC Verification Engineer with expertise in fabric and interconnect verification, spanning both IP and SoC integration. You will play a key role in verifying correctness, performance, and compliance of on‑chip fabrics and interconnect subsystems—from IP bring‑up through full chip integration.

Responsibilities

• Responsible for ASIC design verification of fabric and interconnect IP blocks as well as full‑chip integration, covering DMA, routing, arbitration, ordering, flow control, and protocol compliance.
• Develop and implement test plans for fabric and interconnect verification of SoCs using UVM‑based environments, targeting both IP‑level and system‑level scenarios.
• Design and implement constrained‑random and directed SystemVerilog testbenches for interconnect fabrics, network‑on‑chip (NoC) topologies, and multi‑agent SoC integrations.
• Collaborate extensively with Architecture, SW/FW, Design, Modeling, Emulation, and Post‑Silicon Validation teams to ensure comprehensive first‑time‑right verification plans and execution.
• Drive the development of silicon and platform verification strategies and methodologies for fabric and interconnect subsystems.

Qualifications

• B.S. or M.S. degree in Computer Engineering, Electrical Engineering, or a related field (or equivalent experience).
• 8+ years of experience in ASIC verification, with a strong focus on fabric, interconnect, or network‑on‑chip verification at both IP and full‑chip levels.

Skills

• Strong knowledge of SystemVerilog and UVM methodology.
• Hands‑on experience with industry‑standard interconnect and bus protocols (e.g., AMBA AXI, CHI, or equivalent), including ordering, coherency, and flow‑control semantics.
• Familiarity with SoC architectures, NoC topologies, and multi‑initiator/multi‑target interconnect designs.
• Proficiency in scripting languages such as Python, Perl, or TCL.
• Knowledge of performance verification and bandwidth/latency analysis for interconnect fabrics (a plus).
• Exposure to verification IPs for bus protocols or emulation platforms (e.g., Palladium, Veloce) for full‑chip fabric validation (a plus).
• Experience in GPU or AI accelerator SoC interconnect verification (desirable).
• Experience with formal verification or assertion‑based verification (SVA) applied to fabric and protocol properties (a plus).

Benefits

• Highly competitive salaries.
• Comprehensive benefits package (see www.nvidiabenefits.com).
• Eligibility for equity awards.

Pay

• Base salary range for Level 4: $168,000 – $264,500 USD.
• Base salary range for Level 5: $196,000 – $310,500 USD.