CPU Core Design Verification Testbench Lead

Who You Are

• You bring 8+ years in CPU verification, CPU testbench development, or closely related digital design.
• You have deep hands-on experience building and owning CPU core-level testbenches, not just using existing environments.
• You know high-performance out-of-order CPU microarchitecture in depth.
• You are comfortable developing testbench infrastructure in CVM methodology, with UVM experience as a strong plus.
• You work comfortably across RTL, waveforms, logs, regressions, and cross-functional debug with design, DV, emulation, and post-silicon teams.
• You are comfortable using AI-assisted verification workflows to improve debug, stimulus creation, and coverage analysis, while applying strong engineering judgment to validate results.

What We Need

• Lead hands-on CPU core-level testbench development for high-performance out-of-order RISC-V cores.
• Own and evolve CVM-based verification methodology, infrastructure, and reusable testbench components.
• Plan and drive functional verification for CPU core features, ISA behavior, and microarchitectural scenarios.
• Develop UVM, assembly, C/C++ stimulus, and C++ functional models for RISC-V extensions and un-core components such as APIC and IOMMU.
• Debug regressions, close coverage, and improve core, cluster, and chip-level testbenches across simulation, emulation, and post-silicon environments.
• Develop testbench and tooling infrastructure that combines Python orchestration with specialized AI agents to accelerate triage and root-cause analysis across logs, waveforms, and verification databases.

What You Will Learn

• How Tenstorrent designs and validates high-performance RISC-V CPU cores and clusters.
• Techniques for building scalable CPU testbench infrastructure across core, cluster, and chip-level environments.
• Ways to apply CVM methodology to complex CPU verification and debug workflows.
• Techinques for spanning pre-silicon, emulation, and post-silicon verification with shared stimulus.
• How to scale coverage, debug, and infrastructure across multiple CPU programs within Tenstorrent’s broader compute roadmap.
• How Tenstorrent applies AI across the DV lifecycle — from test planning and stimulus through regression debug, triage, and coverage analysis — using workflows designed to keep context tight and outputs auditable.