CPU Core Design Verification Test Generator Lead

Who You Are

• Bring 8+ years in CPU design verification, test generation, or closely related CPU validation work.
• Led development of test generators for x86, ARM, or RISC-V ISA environments.
• Understand CPU ISA behavior, privileged architecture, and high-performance out-of-order CPU microarchitecture.
• Comfortable building tools, stimulus, and automation that scale verification across large CPU programs.
• Communicate clearly across design, DV, architecture, emulation, and post-silicon teams.

What We Need

• Lead development of CPU core-level test generators for high-performance out-of-order RISC-V cores.
• Own generator strategy, infrastructure, and methodology for ISA and microarchitectural verification in both pre-silicon and post-silicon.
• Develop directed and randomized stimulus that targets architectural corner cases, instruction interactions, and complex CPU behavior.
• Support RISC-V certification work, including test content, compliance flows, debug, and closure.
• Guide a small team of 4-5 engineers while staying hands-on with implementation, debug, and verification execution.

What You Will Learn

• How Tenstorrent designs and validates high-performance RISC-V CPU cores and clusters.
• Techiques for scaling CPU test generator infrastructure across core, cluster, and chip-level environments.
• Ways to apply ISA-driven stimulus to complex CPU verification and debug workflows.
• Techniques for supporting RISC-V certification alongside internal verification requirements.
• Techniques for scaling coverage, debug, and generator methodology across multiple CPU programs within Tenstorrent’s broader compute roadmap.