CPU Clock Design Engineer

About the role

Join a Team That Defines the Heartbeat of Next-Generation CPUs Intel is seeking passionate engineers to help develop the clocking architecture that powers our next-generation CPU products. Whether you're a college graduate eager to launch your career or an experienced engineer ready to solve some of the industry's most complex technical challenges, you'll have the opportunity to work on cutting-edge semiconductor technologies that impact millions of devices worldwide. As a CPU Clock Design Engineer you will contribute to the design, implementation, analysis, and optimization of clock distribution networks that enable industry-leading performance, power efficiency, and product scalability.

Responsibilities

• Design, implement, and optimize clock distribution networks for high-performance CPU and SoC products.
• Contribute to clock architecture development and clock tree synthesis (CTS) methodologies.
• Perform timing analysis and support timing closure across complex semiconductor designs.
• Develop custom circuits, library cells, and clock-related design solutions.
• Analyze performance, power, area, and timing tradeoffs to improve product efficiency.
• Create automation solutions using scripting and programming languages to improve design productivity.
• Collaborate closely with architecture, design, physical implementation, validation, and EDA teams.
• Support debug, validation, and optimization activities throughout the product development lifecycle.
• Drive technical issues to closure while maintaining high-quality engineering standards.
• Influence future methodologies, design flows, and clocking technologies.

Requirements

Bachelor's degree in Electrical/Computer Engineering, Computer Science, or a related STEM field with 3+ years of experience. Or a Masters in the same field with 1+ years of educational or work experience. Your experience listed above must be in three or more of the following: Digital circuit design, VLSI design, Physical design, Clock tree synthesis (CTS), Static timing analysis (STA), Logic design, Custom circuit design, Semiconductor design methodologies, Experience with one or more programming or scripting languages such as Python, Perl, TCL, Shell, or similar.

Qualifications

PhD in Electrical/Computer Engineering, or related field. Hands on experience in high frequency custom clock network design on leading edge technology nodes. Experience in clocking architecture, PLL/DLL architecture and design. Expertise in timing constraint adaptation and timing closure methodologies. Expertise in fullchip design tools and flows.

Skills

• Strong ownership and accountability for technical deliverables.
• Curiosity and passion for solving complex engineering challenges.
• Effective problem-solving and analytical thinking skills.
• Ability to collaborate across multiple engineering disciplines.
• Strong communication skills with both technical and non-technical stakeholders.
• Adaptability and willingness to learn new tools, technologies, and methodologies.
• Ability to balance multiple priorities in a fast-paced environment.
• Continuous focus on quality, execution, and innovation.

Benefits

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.

Pay

Annual Salary Range for jobs which could be performed in the US: $105,650.00 - 269,100.00 USD. The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.

Schedule

Shift Job Type: Shift 1 (United