CPU Cache Subsystem Senior Design Manager

In most instances, this position requires in‑person interviews. Applicants may indicate a preferred working location from Austin, TX; Mountain View, CA; Portland, OR; or Poughkeepsie, NY.

Minimum qualifications

• Bachelor's degree in Electrical Engineering, Computer Science, or equivalent practical experience.
• 15 years of experience in CPU design, including load‑store unit logic/RTL and L2/L3 private/shared caches, micro‑architecture definition and PPA processing.
• Experience leading and managing teams for modern processor subsystems with high‑speed, lower‑power design.
• Experience with front‑end quality checks (e.g., Lint, CDC/RDC).

Preferred qualifications

• Experience with ARM instruction set architecture.
• Experience with mobile CPU subsystem.
• Experience with mobile SOC architecture/integration.

About the role

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct‑to‑consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

In this role you will contribute to all phases of complex designs of CPU subsystems—from design specification to productization, including integration into target SoCs. You will lead and manage a front‑end design team, collaborate with architecture, software, verification, power, DFT, and physical design teams to define the micro‑architecture and schedule, delivering high‑quality RTL that meets project goals. You will help your team grow and solve technical problems with innovative micro‑architecture and practical logic solutions, evaluating design options with complexity, performance, power, area, and schedule in mind.

Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, software, and hardware to create radically helpful experiences, researching, designing, and developing new technologies and hardware to make computing faster, seamless, and more powerful.

Responsibilities

• Lead and manage a team of design engineers working on CPU functional units, emphasizing micro‑architecture and RTL design for the next‑generation CPU subsystem.
• Review and propose performance‑enhancing micro‑architecture features; collaborate with software, architecture, and performance teams for trade‑off studies and communicate pros and cons.
• Deliver plans to achieve project milestones and goals, ensuring production‑quality design on schedule.
• Work with verification, physical design, and power teams to meet frequency, power, and area targets.
• Focus on load‑store‑unit and cache subsystem design and optimizations with other CPU parts to deliver optimal performance, power, and area (PPA).

Pay

US: $240,000 – $333,000 (USD) plus a 25% bonus target, equity, and benefits.