Clocking Architect

About the role

The Clocking Architect will lead the definition, design, and integration of clocking architectures for Altera's next-generation FPGA and SoC devices. Responsibilities include owning the end-to-end clocking strategy, defining subsystem-level clocking plans, establishing clock gating policies, and delivering comprehensive clocking specifications.

Responsibilities

• Own and drive the complete clocking architecture for Altera’s FPGA/SoC devices, including clock tree topology, domain partitioning, frequency planning, and PLL/DLL resource allocation.
• Define subsystem-level clocking plans aligned with chip-level power budgets, protocol timing margins, and physical implementation constraints.
• Establish clock gating policies, low-power clocking methodologies, and dynamic frequency scaling strategies.
• Deliver the clocking specification, clock architecture diagrams, and constraint management documentation as program-level deliverables.
• Collaborate with RTL, physical design, timing, and verification teams to ensure the clock architecture is correctly modeled and implemented across all design stages.

Requirements

• Deep hands-on expertise in PCIe, High-Speed Memory I/O, ARM, Ethernet, and SerDes clocking domains, combined with mastery of SDC constraint authoring for both functional and DFT modes.
• Proven ownership of full-chip and subsystem-level clocking architecture on high-complexity SoC or FPGA devices.
• Expert-level experience architecting clocking for ML/AI accelerator silicon: multi-frequency compute/memory/interconnect clock planes, DVFS, and HBM/LPDDR5X integration.
• Comprehensive DFT clocking experience: scan, ATPG, OCC, MBIST, LBIST, and associated SDC methodology.
• Experience with low-power design methodologies (UPF/CPF) and their interaction with clock gating and multi-voltage power domains.

Qualifications

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related technical field.
• 12+ years of industry experience in physical design, SoC/FPGA design, or clocking architecture, with silicon tape-outs at 7nm or below.
• Proven ownership of full-chip and subsystem-level clocking architecture on high-complexity SoC or FPGA devices.
• Deep expertise across PCIe (Gen4/5/6), DDR5/LPDDR5/HBM, ARM CoreLink/CMN, Ethernet (1G–400G), Configuration interfaces, and SerDes clocking.
• Expert-level CDC architecture ownership: full-chip CDC planning, synchronizer strategy, metastability analysis, and end-to-end CDC sign-off.
• Proficiency with CDC verification tools (SpyGlass CDC, JasperGold CDC, Questa CDC) including waiver management and RTL coding guideline enforcement.
• Expert-level SDC constraint authoring and validation using Synopsys PrimeTime and/or Cadence Tempus.
• Experience with low-power design methodologies (UPF/CPF) and their interaction with clock gating and multi-voltage power domains.

Skills

• Expert-level SDC constraint authoring and validation using Synopsys PrimeTime and/or Cadence Tempus.
• Experience with low-power design methodologies (UPF/CPF) and their interaction with clock gating and multi-voltage power domains.
• Experience with formal CDC verification and model checking (VC Formal) for synchronizer correctness proofs.
• Familiarity with PLL/DLL characterization, frequency margining, jitter budget analysis, and SSC validation.
• Knowledge of IEEE 1500, P1687 (IJTAG), and their clocking implications for embedded DFT instrumentation.
• Experience with multi-die/chiplet clocking architectures (UCIe, BoW, AIB) and die-to-die CDC management.
• Scripting proficiency in Tcl and/or Python for constraint automation, CDC report parsing, and custom analysis flows.
• Familiarity with Intel/Altera FPGA architecture (Stratix, Agilex product families) a significant advantage.

Benefits

Comprehensive benefits: medical, dental, vision, 401(k) with company match, and paid parental leave.

A flexible hybrid work model and dedicated professional development investment.

Access to Altera’s world-class EDA infrastructure, IP libraries, and advanced process node programs.

Pay

$187,000 - $270,700 USD

Schedule

Shift 1 (United States of America)

Primary Location

San Jose, California, United States